This paper reviews and analyzes well-known countermeasures against distributed denial of service (DDoS) attacks. This paper provides an in-depth analysis of each countermeasure and enumerates ...strengths and challenges of each technique. If it is possible, the paper designs a countermeasure against each defense mechanism from the attacker’s point of view. We believe that this survey is the most complete survey that analyzes the most cited DDoS defense techniques in detail. We expect that this survey will assist the potential victims to choose suitable countermeasures against DDoS attacks based on the analysis presented here and as well as the capabilities that they have to implement the techniques. The analysis done in this paper provides a great opportunity for both academic and industrial researchers to improve the state of the art countermeasures against DDoS attacks.
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GEOZS, IJS, IMTLJ, KILJ, KISLJ, NUK, OILJ, PNG, SAZU, SBCE, SBJE, UL, UM, UPCLJ, UPUK
Emerging cellular networks integrate diverse technologies like millimeter wave (mmWave) to deliver high capacity but face challenges like blockage sensitivity. Dual connections (DC) enhance ...throughput but ensuring information freshness (Age-of-Information, AoI) is crucial for real-time applications. This paper proposes a novel approach for AoI optimization in DC cellular networks (4G/5G) with TCP multipath transport. We address the stochastic nature of AoI and channel conditions with a combined random and stochastic optimization approach. Modeling the system as a multi-queue system with LTE and mmWave connections, we propose a difference learning-based algorithm that dynamically selects the optimal queue for each packet. This eliminates the need for statistical information like packet arrival rates, enabling real-time adaptation. Compared to existing methods, our algorithm significantly reduces AoI under various network conditions (over 40%), demonstrating its effectiveness for real-time applications.
In an application-layer distributed denial of service (App-DDoS) attack, zombie computers bring down the victim server with valid requests. Intrusion detection systems (IDS) cannot identify these ...requests since they have legal forms of standard TCP connections. Researchers have suggested several techniques for detecting App-DDoS traffic. There is, however, no clear distinction between legitimate and attack traffic. In this paper, we go a step further and propose a Machine Learning (ML) solution by combining the Radial Basis Function (RBF) neural network with the cuckoo search algorithm to detect App-DDoS traffic. We begin by collecting training data and cleaning them, then applying data normalizing and finding an optimal subset of features using the Genetic Algorithm (GA). Next, an RBF neural network is trained by the optimal subset of features and the optimizer algorithm of cuckoo search. Finally, we compare our proposed technique to the well-known k-nearest neighbor (k-NN), Bootstrap Aggregation (Bagging), Support Vector Machine (SVM), Multi-layer Perceptron) MLP, and (Recurrent Neural Network) RNN methods. Our technique outperforms previous standard and well-known ML techniques as it has the lowest error rate according to error metrics. Moreover, according to standard performance metrics, the results of the experiments demonstrate that our proposed technique detects App-DDoS traffic more accurately than previous techniques.
Distributed Denial of Service (DDoS) attacks are a growing threat to online services, and various methods have been developed to detect them. However, past research has mainly focused on identifying ...attack patterns and types, without specifically addressing the role of freely available DDoS attack tools in the escalation of these attacks. This study aims to fill this gap by investigating the impact of the easy availability of DDoS attack tools on the frequency and severity of attacks. In this paper, a machine learning solution to detect DDoS attacks is proposed, which employs a feature selection technique to enhance its speed and efficiency, resulting in a substantial reduction in the feature subset. The provided evaluation metrics demonstrate that the model has a high accuracy level of 99.9%, a precision score of 96%, a recall score of 98%, and an F1 score of 97%. Moreover, the examination found that by utilizing a deliberate approach for feature selection, our model's efficacy was massively raised.
In an application-layer distributed denial of service (DDoS) attack, zombie machines send a large number of legitimate requests to the victim server. Since these requests have legitimate formats and ...are sent through normal TCP connections, intrusion detection systems cannot detect them. In these attacks, an adversary does not saturate the bandwidth of the victim server through inbound traffic, but through outbound traffic. The next aim of the adversary is to consume and exhaust computational resources (e.g., CPU cycles), memory resources, TCP/IP stack, resources of input/output devices, etc. This paper proposes a novel scheme which is called ConnectionScore to resist such DDoS attacks. During the attack time, any connection is scored based on history and statistical analysis which has been done during the normal condition. The bottleneck resources are retaken from those connections which take lower scores. Our analysis shows that connections established by the adversary give low scores. In fact, the ConnectionScore technique can estimate legitimacy of connections with high probability. The rate of suspicious connections being dropped is adjusted based on the current level of overload of the server and a threshold-level of free resources. To evaluate the performance of the scheme, we perform experiments in the Emulab environment using real traceroute data of the ClarkNet WWW server (
http://ita.ee.lbl.gov/html/contrib/ClarkNet-HTTP.html
).
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EMUNI, FIS, FZAB, GEOZS, GIS, IJS, IMTLJ, KILJ, KISLJ, MFDPS, NLZOH, NUK, OBVAL, OILJ, PNG, SAZU, SBCE, SBJE, SBMB, SBNM, UKNU, UL, UM, UPUK, VKSCE, ZAGLJ
Aging mechanisms in FPGA devices cause performance degradation and lead to lifetime reduction. Among multiple aging mechanisms, Biased-Temperature-Instability (BTI) aging mechanism is the dominant ...one. BTI decreases the Static-Noise-Margin (SNM) of SRAM cells leading to more Soft-Error-Rate (SER) and lower SRAMs’ stability in FPGAs. This paper proposes the BAS (BTI Aware Synthesis), a three-step post-synthesis and pre-place-and-route tool to reduce the impact of BTI in FPGA’s LUTs significantly using the Bit-Flipping and Boolean Matching techniques. BAS receives a standard EDIF format synthesis output file from a synthesis tool (e.g., C.edf) and finally creates two output EDIF files with the same functionality as the original input file (e.g., C1.edf and C2.edf), while all LUT SRAMs contents are mutually flipped. The two BTI-Aware-created EDIF synthesis files are periodically used for FPGA’s reconfiguration. Our experimental results demonstrates that BAS improves SNM and SER on average by 16.1% and 15.7% compared to previous state-of-the-art techniques, respectively. BAS has two main advantages over previous state-of-the-art techniques: (1) it is more flexible and applicable as an embedded tool within worldwide commercial synthesis tools, and (2) unlike the previous state-of-the-art techniques, it does not need the map and details of the FPGAs.
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GEOZS, IJS, IMTLJ, KILJ, KISLJ, NLZOH, NUK, OILJ, PNG, SAZU, SBCE, SBJE, UILJ, UL, UM, UPCLJ, UPUK, ZAGLJ, ZRSKP
The multilayer structure of 3-D network-on-chips (3-D NoC) leads to the unequal thermal conductance between different layers and, as a result, an unbalanced thermal distribution in the chip. This ...issue leads to the low reliability and performance degradation of 3-D NoCs. To ensure thermal safety, 3-D NoCs require effective cooling methods. Several thermal-aware routing algorithms have been proposed to route packets in a way which helps mitigation of imbalance temperature distribution. To have a thermal-aware path selection and safety thermal distribution, we propose a new thermal-aware routing method based on the Q-learning algorithm (Q-Thermal). In our method, thermal information propagates over the network using ordinary network packets. Thanks to the Q-learning algorithm that keeps always the thermal information of routers up-to-date that causes routers steer packets toward the cooler paths (laterally or vertically). Based on the experimental results, Q-Thermal reduces the heat and temperature of different layers of 3-D NoCs significantly in comparison with the previous state-of-the-art techniques. Q-Thermal leads to a balanced thermal distribution in the stacked layers of the chip and it improves the network performance considerably.
In recent years, hardware sorters have been an attracted topic for researchers. Since hardware sorters play a crucial role in embedded systems, several attempts have been made to efficiently design ...and implement these sorters. Previous state-of-the-art hardware sorters are not suitable for embedded edge computing devices because they (1) consume high power, (2) occupy high area, (3) work for limited data-width numbers, (4) require many memory resources, and (5) finally, their architecture is not scalable with the number of input records. This paper proposes a hardware sorter for edge devices with limited hardware resources. The proposed hardware sorter, called Edge-Sorter, processes 4 bits of input records at each clock cycle. Edge-Sorter utilizes the unary processing in its main processing core. Edge-Sorter has valuable attributes compared to previous state-of-the-art techniques, including low power consumption, low area occupation, sorting numbers without storing their indices, sorting numbers with arbitrary data-width, and scalable with the number of input records. The proposed approach is evaluated and compared with previous state-of-the-art techniques with two different implementation and synthesis environments: Xilinx Vivado FPGA-based and Synopsys Design Compiler 45-nm ASIC-based. The Synthesis results of both environments indicate that both Edge-Sorter techniques reduces area and power consumption on average by 80% and 90%, respectively compared to previous techniques.
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GEOZS, IJS, IMTLJ, KILJ, KISLJ, NLZOH, NUK, OILJ, PNG, SAZU, SBCE, SBJE, UILJ, UL, UM, UPCLJ, UPUK, ZAGLJ, ZRSKP
10.
HRHS: A High-Performance Real-Time Hardware Scheduler Derafshi, Danesh; Norollah, Amin; Khosroanjam, Mohsen ...
IEEE transactions on parallel and distributed systems,
2020-April-1, 2020-4-1, Volume:
31, Issue:
4
Journal Article
Peer reviewed
This article represents an on-line time-predictable distributed hardware scheduler solution, suitable for many-core systems. We have partitioned the Main scheduler into uniform Partial schedulers to ...achieve a significant gain in term of performance and scalability, while software scheduling solutions impose excessive delays (in order of thousands of clock cycles) to a system. Although we have considered the implementation of the Earliest Deadline First (EDF) algorithm for each Partial scheduler, one can use customized scheduling policies, as needed. Designers can also modify different parts of our proposed architecture to obtain more suitable hardware for their design. HRHS outperforms conventional schedulers, in terms of resource utilization (LUT, register), delay and energy consumption by 36.83, 22.93, 46.36 and 59.26 percent on average, respectively. It also overpowers clustering solutions by circumventing their intrinsic off-line characteristics. The presented designs are also implemented in ASIC with 45-nanometer technology, in which the HRHS design excels in power, area and critical path length by 49.33, 50.67, and 53.33 percent on average, respectively, over other designs implemented in this article.
