Processor customisation is an effective technique to enhance performance across an application domain. In this study, the authors present a new customised soft processor development environment ...called polytechnique customised soft processor (PolyCuSP), which bridges the gap between architecture description languages (ADLs) and extensible soft processors. The main objective of this environment is to facilitate rapid design space exploration while preserving a wide range of customisation flexibility. For this purpose, PolyCuSP offers full flexibility in instruction-set description, while limiting the datapath customisation to a predefined set of tunable microarchitectural parameters. The environment avoids extensive datapath description that is unnecessary for usual microarchitectural customisation techniques in order to simplify the development process. A new XML-based description format is introduced for instruction-set modelling. Experimental results evaluate and compare the design and customisation complexities offered by PolyCuSP with competitive approaches. Results demonstrate the efficiency of applying customisation techniques in the proposed environment. For the Sobel edge detection algorithm, the results show that microarchitectural tuning and instruction-set architecture customisation improve the performance-per-cost ratio by an average of 44 and 27%, respectively. Furthermore, in a case study of a tone-mapping algorithm, PolyCuSP achieves an average improvement of 38% in performance-per-cost ratio over an ADL-based design applying the same customisations.
Full text
Available for:
DOBA, FZAB, GIS, IJS, KILJ, NLZOH, NUK, OILJ, SAZU, SBCE, SBMB, UILJ, UKNU, UL, UM, UPUK
In the aerospace industry, as the modern avionics systems became more and more complex, the Integrated Modular Avionics (IMA) architecture has been proposed as a replacement of the federated ...architecture, in order to offer better solutions on SWaP constraints (Size, Weigh and Power). However, the development process of IMA avionics systems is much more difficult. This paper aims to propose to the aerospace industry a set of time-effective and cost-effective solutions for the integration and functional validation of IMA systems.
Based on MBE methodology, which is considered as an interesting solution for the IMA systems development 8, this paper proposes a design flow, that integrates three steps of refinement, for the configuration and the validation of IMA platforms. In the first step of the design flow, the modeling language AADL is used to describe the IMA architecture. The AADL modeling environment OCARINA, a code generator initially designed for the real-time operating system POK, has been modified to generate software integration code and system configuration files for the IMA simulator named SIMA. This solution is a cost effective alternative to expensive commercial development environments to validate ARINC653 software applications. In the second step of the design flow, a cosimulation platform composed of two simulators is proposed: Simulink for the simulation of peripherals and SIMA for the simulation of IMA modules. In the third step, the validated avionics applications and system configuration can be ported with minimum effort from the cosimulation environment to an implementation platform.
A case study, which consists in integrating several avionics applications to SIMA and then porting them to PikeOS development environment, was brought in the purpose of demonstrating the proposed design flows and co-simulation platform. The research work realized in this paper is a part of collaboration between industrials and academics through the CRIAQ AVIO509 project.
Spacecraft pose estimation is an essential computer vision application that can improve the autonomy of in-orbit operations. An ESA/Stanford competition brought out solutions that seem hardly ...compatible with the constraints imposed on spacecraft onboard computers. URSONet is among the best in the competition for its generalization capabilities but at the cost of a tremendous number of parameters and high computational complexity. In this paper, we propose Mobile-URSONet: a spacecraft pose estimation convolutional neural network with 178 times fewer parameters while degrading accuracy by no more than four times compared to URSONet.
This paper describes an application-specific instruction set for a configurable processor to accelerate motion-compensated frame rate conversion (MC-FRC) algorithms based on block motion estimation ...(BME). The paper shows that the key to achieve very high performance when creating new instructions is to leverage, at the same time, parallel computations, data reuse, and efficient cache use. This is supported by concrete examples that demonstrate how it can be done in the case of the two algorithms considered. The new instructions are used to implement two BME algorithms: one implements the full search (FS) block matching algorithm (BMA), while the other implements the One-Dimensional Full Search (ODFS) BMA. The obtained acceleration factors exceed one hundred for the MC-FRC algorithm embedding the FS algorithm and twenty for the ODFS algorithm. The results show that getting such global acceleration is the consequence of combining parallel computations, data reuse, and efficient cache use, not of only one of them.
Full text
Available for:
EMUNI, FIS, FZAB, GEOZS, GIS, IJS, IMTLJ, KILJ, KISLJ, MFDPS, NLZOH, NUK, OILJ, PNG, SAZU, SBCE, SBJE, SBMB, SBNM, UKNU, UL, UM, UPUK, VKSCE, ZAGLJ
This paper introduces a new approach for finite-precision error modeling based on affine arithmetic. The paper demonstrates that there is a common hazard in affine arithmetic-based error modeling ...methods described in the literature. The hazard is linked to early substitution of the signal terms that emerge in operations such as multiplication and division. The paper proposes postponed substitution combined with function maximization to address this problem. The paper also proposes a modification in the error propagation process to enhance the error modeling accuracy. An existing word length optimization method is reproduced to evaluate the efficiency of this modification. The results demonstrate that the proposed modification can improve the hardware area results by up to 7.0% at the expense of negligible complexity overhead.
Optical network-on-chip (ONoC) architectures are emerging as promising contenders to solve bandwidth and latency issues in multiprocessor systems-on-chip (MPSoC). However, current on-chip integration ...technologies for optical interconnect allow interconnecting only dozens of IPs. Scaling with MPSoCs composed of hundreds of IPs thus, relies on unpredictable technological innovations. In this letter, we propose a method that combines multiple ONoCs. Each ONoC is small enough to rely on already existing and proven technologies. We evaluate the approach for various interconnect scenarios, showing that it scales well with the size of the MPSoC architectures.
La Radio Pío XII de Siglo XX en Bolivie a été financée en bonne partie par les catholiques du Québec pour combattre l'alcoolisme, l'analphabétisme et le communisme. Construite en 1959, elle ...s'inscrivait dans un anti-communisme primaire où l'Occident chrétien affrontait l'Orient communiste et athée. Cette radio devait cependant connaître un revirement radical à partir de 1961 sous la triple pression d'un durcissement des régimes militaires qui allaient se succéder en Bolivie et sur l'ensemble du continent; d'une vaste réforme de l'Église catholique sous l'impulsion de Vatican II dont l'option préférentielle pour les pauvres devait être radicalisée et systématisée pour devenir en Amérique latine la Théologie de la libération; et enfin, d'un monde en pleine ébullition où de Prague à Los Angeles, en passant par La Havane et Paris, on entrait dans une période de turbulence sociale hors de l'ordinaire. Ces jeunes prêtres -Québécois, Américains, Espagnols -devaient être des acteurs importants de ce revirement qu'allait connaître cette radio, dans la région la plus pauvre de Bolivie. Une région où le syndicat des mineurs avait été un des principaux artisans de la révolution bolivienne de 1952 qui avait menée à la nationalisation des mines et à une vaste réforme agraire. La Radio Pío XlI devenait dans ce contexte le lieu à la fois physique et symbolique où s'est cristallisée cette rencontre entre ces prêtres nouveau genre et la résistance bolivienne. Une radio que les militaires ont fait sauter à cinq reprises parce qu'elle planifiait des grèves, organisait des réseaux radiophoniques de résistance aux nombreux coups d'État, cachait des armes et faisait sortir des dissidents clandestinement du pays. Ces prêtres oblats ont été arrêtés, emprisonnés et battus parce qu'ils étaient les protagonistes d'une nouvelle évangélisation dite libératrice, dont la radio constituait le principal outil. L'histoire de la Radio Pío XII et de son revirement inédit seront analysés à travers les concepts d'altérité (Todorov), de l'histoire politique de la chrétienté (monde-plein de Gauchet), de la Théologie de la libération (Gutiérrez et L. Boff) et de l'espace public (Habermas). Une radio qui évoluait dans un microcosme qui concentrait alors les conflits et les contradictions qui traversaient l'ensemble du continent sud-américain (mésocosme). ______________________________________________________________________________ MOTS-CLÉS DE L’AUTEUR : Altérité, Théologie de la libération, Espace public, Monde-plein, Sujets-acteurs.
Analog and mixed signal (AMS) designs are an important part of embedded systems that link digital designs to the analog world. Due to challenges associated with its verification process, AMS designs ...require a considerable portion of the total design cycle time. In contrast to digital designs, the verification of AMS systems is a challenging task that requires lots of expertise and deep understanding of their behavior. Researchers started lately studying the applicability of formal methods for the verification of AMS systems as a way to tackle the limitations of conventional verification methods like simulation. This paper surveys research activities in the formal verification of AMS designs as well as compares the different proposed approaches.
Full text
Available for:
GEOZS, IJS, IMTLJ, KILJ, KISLJ, NUK, OILJ, PNG, SAZU, SBCE, SBJE, UL, UM, UPCLJ, UPUK
Instrumentation methods for code profiling, tracing and semihosting on virtual platforms (VP) and instruction-set simulators (ISS) rely on function call and system call interception. To reduce ...instrumentation overhead that can affect program behavior and timing, we propose a novel low-overhead flexible instrumentation framework called Virtual Platform Instrumentation (VPI). The VPI framework uses a new table-based parameter-passing method that reduces the runtime overhead of instrumentation to only that of the interception. Furthermore, it provides a high-level interface to extend the functionality of any VP or ISS with debugging support, without changes to their source code. Our framework unifies the implementation of tracing, profiling and semihosting use cases, while at the same time reducing detrimental runtime overhead on the target as much as 90% compared to widely deployed traditional methods, without significant simulation time penalty.
Content addressable memories (CAMs) are commonly used in applications requiring high speed access to some data set. This technology allows data items to be accessed in constant time based on content ...rather than on address. Unfortunately this technology has several drawbacks: it occupies more die area per bit, dissipates more power, and has higher latency. Recently, an efficient architecture based on a parallel hashing has been proposed as an alternative to CAM technology. In the present paper, we go a step further by backing preliminary simulation results of this proposed architecture by a complete analytical model. The insertion operations applied on the proposed architecture can be modeled with the balls and urns problem. We also propose a method to identify optimal configuration parameters in order to start designing efficiently. Finally, a VLSI implementation and optimizations of the proposed architecture are presented in order to obtain a more thorough understanding of how it could compare to commercial CAMs. Because of its simple design and of the widely spread use of the required tools, this new architecture offers a very appealing alternative to CAM technology.
PDF
