Recent applications require vertical chip stacking to increase the performance of many devices without the need of advanced node components. Image sensors and vision systems will embed more and more ...smart functions, for instance, image processing, object recognition, and movement detection. In this perspective, the combination of Cu-to-Cu direct hybrid bonding technology with Through-Silicon-Via (TSV) will allow 3D interconnection between pixels and the associated computing and memory structures, each function fabricated on a separate wafer. Wafer-to-wafer hybrid bonding was achieved with multi-pitch design—1–4 μm—of single levels of Cu damascene patterned on 300 mm silicon substrates. Defect-free bonding, as far as the extreme edge of the wafer, was demonstrated on a stack with three wafers. Middle wafers thinning was done with grinding only and with a thickness uniformity (TTV) <2 μm to an ultimate thinning as low as 3 μm. Alignment performance was characterized by post-bonding for two superposed hybrid bonding interfaces. In our set of wafers, modeling the alignment with translation, rotation, and scaling components enables us to optimize the residuals down to 3σ < 100 nm. A process flow of thin TSV with a fine pitch of 2 μm for high-density vertical interconnect through a three-wafer stack was developed. Via-last TSV architecture was adopted with 1 μm TSV diameter and 10 μm thickness. Lithography, etching solutions, Ti/TiN barrier deposition, and void-free Cu filling solutions were demonstrated. TSV cross sections after CMP and connections with top and bottom Cu damascene lines show good profile control. Process developments are matured and can be reliably used in the fabrication of an electrical test vehicle including vertical interconnects associating multi-wafers stacking with a hybrid bonding process and high-density thin TSV applicable to low pitches (<5 μm).
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EMUNI, FIS, FZAB, GEOZS, GIS, IJS, IMTLJ, KILJ, KISLJ, MFDPS, NLZOH, NUK, OILJ, PNG, SAZU, SBCE, SBJE, SBMB, SBNM, UKNU, UL, UM, UPUK, VKSCE, ZAGLJ
SOI circuits exhibit excellent performance and scalability but suffer from self-heating. Systematical 2D simulations demonstrate that the thermal dissipation in SOI MOSFETs can be improved ...dramatically by replacing the buried oxide with high thermal conductance insulators. The self-heating can be reduced by as much as 50–100
°C. Yet, these materials feature high-
K dielectric constant, which also affects the electrical properties: more severe short-channel effects, parasitic capacitances and drain-to-body fringing fields. The conciliation between the thermal and electrical properties of advanced SOI MOSFETs (50
nm long, 10
nm thick) is examined by comparing different SOI materials (air, SiO
2, diamond, AlN, Al
2O
3, SiC) and MOS architectures. We demonstrate the advantage of a ground plane (GP) located under the buried insulator (BOX). Diamond is excellent candidate for relatively thick BOX whereas Al
2O
3 and SiC are suitable for ultra-thin BOX. These novel structures can be fabricated by wafer bonding technology.
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GEOZS, IJS, IMTLJ, KILJ, KISLJ, NUK, OILJ, PNG, SAZU, SBCE, SBJE, UL, UM, UPCLJ, UPUK
The paper describes the impact of pseudo-MOS technique on threshold and flatband voltages, and why the threshold and flatband voltages depend on silicon-on-insulator (SOI) layer thickness. Our ...measurements and simulations suggest that the band-offset-induced depletion beneath the source contact obstructs the local formation of the inversion layer at the SOI/buried oxide interface; this effect becomes significant when the SOI layer thickness is reduced. The SOI layer thickness dependence of flatband voltage is analyzed in a similar manner. The temperature dependence of threshold and flatband voltages is also addressed.
•Double gate structures for channel material and gate stack characterization.•Easy and simple techniques based on the pseudo-MSOFET configuration.•Fast fabrication loop of double gate MOSFET.•Test ...structures for parameter extraction.•Double-gate pseudo-MOSFET for rapid material characterization.
Pseudo-MOSFET delivers a fast, simple and reliable way of characterizing electrically SOI substrates without the need of full CMOS fabrication. However, the information refers to the back interface. Here, to probe the front interface, we extend the concept to a double-gate pseudo-MOSFET. The structure provides a pertinent test vehicle for the characterization and development of transistors channel and gate stack materials in a configuration similar to fully fabricated transistors. We show that the devices with undoped terminals need specialized modeling development to describe the double gate effect. Devices with doped terminals are immediately exploitable for parameter extraction.
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GEOZS, IJS, IMTLJ, KILJ, KISLJ, NLZOH, NUK, OILJ, PNG, SAZU, SBCE, SBJE, UILJ, UL, UM, UPCLJ, UPUK, ZAGLJ, ZRSKP
The pseudo-MOS transistor technique is useful for quick and accurate characterization of as-fabricated silicon-on-insulator wafers. The sample size and probe-pressure effects on the drain current are ...revisited. It is demonstrated that the geometrical factor is significantly affected by the probe-to-edge distance and probe pressure. The correct geometrical factor, reflecting silicon island size, and probe pressure effects, is extracted from systematic experimental results and used to determine the actual carrier mobility.
The electron mobility in silicon-on-insulator (SOI) layers has been extracted from magnetoresistance data measured on a four concentric ring test structure, operating in pseudo-MOS configuration, ...using Kelvin’s technique. Ohmic contacts were fabricated using a thermally evaporated erbium/silver double layer. The relative magnetoresistance versus magnetic field characteristics demonstrated classic quadratic behavior allowing for straightforward extraction of magnetoresistance mobility. The technique does not require any correction to be applied due to contact resistance or geometrical effects. The electron mobility extracted using magnetoresistance technique is discussed and compared with theoretical predictions.
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GEOZS, IJS, IMTLJ, KILJ, KISLJ, NUK, OILJ, PNG, SAZU, SBCE, SBJE, UL, UM, UPCLJ, UPUK
Novel Unibond wafers, with very thin film and buried oxide, are probed with the pseudo-MOSFET method. It is shown that the method is still efficient at high temperature and for ultra-thin (10 nm) ...films. The threshold and flat-band voltages increase in thinner films due to special effects that are revealed by numerical simulations.
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GEOZS, IJS, IMTLJ, KILJ, KISLJ, NUK, OILJ, PNG, SAZU, SBCE, SBJE, UL, UM, UPCLJ, UPUK
Through Silicon Vias (TSV) is a very promising technology in advanced packaging, for the replacement of wire bonding. This technology is becoming mandatory for fully integrated products such as SiP, ...SoP, 3D components integration (e.g memory stacking), or MEMS structure packaging. Different alternatives are currently investigated such as via-first or via-last. Into the via-first family two different approaches can be considered. The TSV's can be done before the FEOL (pre-process approach) or in-between the FEOL and the BEOL (mid process approach). Each solution has advantages and drawbacks depending on the final application in particular. In a first part of this paper the tungsten mid-process TSV technology will be presented and briefly compared to the copper mid-process approaches. Then, the process of the tungsten TSV fabrication will be detailed and morphological characterizations will be presented. We will focus on two specific parts of the process which have been specifically optimized for the tungsten TSV technology: the low temperature insulation oxide and the tungsten deposition-etch back sequence to fill the vias. The results of those optimizations will be presented and discussed. Last, we will introduce the electrical test vehicle used in this work and present the main results regarding via resistances. Some specific recommendations will by proposed in term of design and integration rules in relation with the process constraints.
Total dose effects on silicon on insulator (SOI) UNIBOND wafers are studied via optical second harmonic generation (SHG). This technique is qualitatively compared with the pseudo-MOSFET technique for ...monitoring charges at the interfaces. Optical and electrical methods are combined to separate the contribution of the signal from each interface to the total SHG intensity. Radiation-induced oxide and interface traps increase the interface fields as determined from the SHG signals and the results are compared with electrical measurements.
3D integration of wafers stacking is obtained with a GaN-based wafer integrated on Si substrate and CMOS wafer. In this study, after planarization of the incoming wafers prior the bonding, ...wafer-to-wafer hybrid bonding technology was provided with a mirror design of Cu patterns embedded in silica matrix to provide direct 3D links in a face-to-face scheme with a low pitch of 3 \mu\mathrm{m} . Then, 1 \mu\mathrm{m} Cu TSV-last patterned through the SOI substrate of the CMOS wafer with and AlCu routing lines was followed with copper pillars in order to connect the stack to the package. We present morphological and electrical characterizations of a test vehicle including a Cu/SiO2 hybrid bonding interface. Scanning Acoustic Microscopy, FIB-SEM and TEM cross-sections demonstrated both a perfect SiO 2 /SiO 2 bonding as well as an excellent Cu/Cu connection validated with electrical data.
