How language is encoded by neural activity in the higher-level language areas of humans is still largely unknown. We investigated whether the electrophysiological activity of Broca’s area correlates ...with the sound of the utterances produced. During speech perception, the electric cortical activity of the auditory areas correlates with the sound envelope of the utterances. In our experiment, we compared the electrocorticogram recorded during awake neurosurgical operations in Broca’s area and in the dominant temporal lobe with the sound envelope of single words versus sentences read aloud or mentally by the patients. Our results indicate that the electrocorticogram correlates with the sound envelope of the utterances, starting before any sound is produced and even in the absence of speech, when the patient is reading mentally. No correlations were found when the electrocorticogram was recorded in the superior parietal gyrus, an area not directly involved in language generation, or in Broca’s area when the participants were executing a repetitive motor task, which did not include any linguistic content, with their dominant hand. The distribution of suprathreshold correlations across frequencies of cortical activities varied whether the sound envelope derived from words or sentences. Our results suggest the activity of language areas is organized by sound when language is generated before any utterance is produced or heard.
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In this paper, a 90-nm 128-Mcell non-volatile memory based on phase-change Ge 2 -Sb 2 -TeB alloy is presented. Memory cells are bipolar selected, and are based on a /xtrench architecture. ...Experimental investigation on multi-level cell (MLC) storage is addressed exploiting the chip MLC capability. To this end, a programming algorithm suitable for 2 bit/cell storage achieving tightly placed inner states (in terms of cell current or resistance) is proposed. Measurements showed the possibility of placing the required distinct cell current distributions, thus demonstrating the feasibility of the MLC phase-change memory (PCM) storage concept. Endurance tests were also carried out. Cumulative distribu tions after 2-bit/cell programming before cycling and after 100 k program cycles followed by 1 h/150 degC bake are presented. Experimental results on MLC endurance are also provided from a 180-nm 8-Mb PCM demonstrator with the same mutrench cell structure.
A subthreshold input voltage charge pump based on the well-known cross-coupled voltage doubler and using boosted gate voltages for the transfer switches is presented. A level shifter and some ...inverters, including a novel inverter architecture proposed in this work and referred to as negative low-state voltage inverter, are used to generate the clock signals for the switching transistors with the purpose of significantly improving their drive capability. A complete analysis of the proposed charge pump is provided to highlight the advantages of the implemented structure, revealing the power efficiency improvement when the input voltage is below the threshold voltage of the transistors. An extensive experimental characterization of silicon prototypes in 180 nm CMOS technology was carried out, showing that the proposed scheme is able to pump charge from an input voltage as low as 110 mV. The experimental peak efficiency remains above 70% for input voltages between 180 mV and 400 mV and input power levels from 45 nW to 25 <inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula>, which are appropriate for different miniaturized transducers implementable on chip.
In the frame of power electronics applications, the request for smart and reconfigurable devices is pushing integration technologies in the direction of embedded systems. In this scenario, ...microcontrollers play a key role, and the availability of embedded non-volatile memory (eNVM) to store the microcontroller code has become crucial to enable real-time customization and increase system flexibility. Among emerging NVMs, phase change technology is becoming a very attractive solution for the development of applications for smart power and automotive markets. In this paper, a 32-KB embedded phase change memory (ePCM) designed and manufactured in 0.11μm smart power BCD technology with a specifically optimized Ge-rich Ge-Sb-Te (GST) alloy (supply voltage = 1.8 V) is presented. Thanks to the use of a differential sensing scheme, the proposed ePCM features 18-ns random access time with improved robustness against resistance drift. The word modify time under 32-cell programming parallelism was kept as low as 20μs, thanks to enhanced programming circuits. The size of the 32-KB eNVM is about 0.7 mm 2 .
In this paper, the feasibility of partial-RESET programming in phase-change memories is experimentally investigated by considering both the single-cell behavior and the effects of parameter spreads ...over a memory array. The aim of this paper is to highlight advantages and drawbacks of partial-RESET programming from the viewpoint of multilevel (ML) storage. Although high reproducibility of a partial-RESET programming curve of a single cell has been observed, the parameter spreads over the array imply the need for a program-and-verify (P&V) approach to achieve the necessary accuracy for ML storage. In order to demonstrate the feasibility of partial-RESET ML programming, 4 log-spaced levels within the available resistance window have been programmed by means of a staircase-up P&V algorithm.
Charge pumps (CPs) represent the most common solution for the implementation of fully integrated DC–DC converters. In fact, as opposed to buck/boost DC–DC converters, that need at least an external ...inductor, charge pump circuits do not require any external component. However, the achievable power efficiency of these circuits is typically significantly lower than power efficiency of buck/boost DC–DC converters. In this study, we develop a general mathematical model of CPs, aiming to provide basic design considerations for power efficiency optimisation. A quality factor for achievable power efficiency is proposed together with guidelines for the design of efficiency-optimised CPs under the constraint of given output voltage and current values.
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Physical unclonable function (PUF) leverages the immensely complex and irreproducible nature of physical structures to achieve device authentication and secret information storage. To enhance the ...security and robustness of conventional PUFs, reconfigurable physical unclonable functions (RPUFs) with dynamically refreshable challenge-response pairs (CRPs) have emerged recently. In this paper, we propose two novel physically reconfigurable PUF (P-RPUF) schemes that exploit the process parameter variability and programming sensitivity of phase change memory (PCM) for CRP reconfiguration and evaluation. The first proposed PCM-based P-RPUF scheme extracts its CRPs from the measurable differences of the PCM cell resistances programmed by randomly varying pulses. An imprecisely controlled regulator is used to protect the privacy of the CRP in case the configuration state of the RPUF is divulged. The second proposed PCM-based RPUF scheme produces the random response by counting the number of programming pulses required to make the cell resistance converge to a predetermined target value. The merging of CRP reconfiguration and evaluation overcomes the inherent vulnerability of P-RPUF devices to malicious prediction attacks by limiting the number of accessible CRPs between two consecutive reconfigurations to only one. Both schemes were experimentally evaluated on 180-nm PCM chips. The obtained results demonstrated their quality for refreshable key generation when appropriate fuzzy extractor algorithms are incorporated.
This brief presents a system architecture designed to enable 1-bit-per-cell storage in Ge-rich phase change memory (PCM) even in the presence of the resistance drift of the low-resistance (SET) ...state, thus overcoming the intrinsic low storage density (half bit per cell) of the currently used differential solutions. The read reference current is automatically adjusted to best exploit the reading window between the RESET and the SET state that changes over time. The working principles of the system are presented, discussed, and experimentally validated. The proposed system was implemented exploiting a 110-nm BCD embedded PCM test chip and successfully tested in the temperature range from -40 °C to +150 °C.
In this paper, we examine the problem of the drift of the low-resistance state (LRS) in phase change memories based on C or N doped and undoped Ge-rich Ge 2 Sb 2 Te 5 . A novel procedure, named R-SET ...technique, is proposed to boost the SET speed of these innovative phase change materials by overcoming the decrease of crystallization speed caused by Ge enrichment. The R-SET technique allows, at the same time, an optimized SET programming of the memory cell and the reduction of the LRS drift with respect to standard SET procedures. A circuit that generates the desired R-SET pulse based on a time reference scheme is proposed and discussed.
This paper presents a novel approach for the modeling and the simulation of a phase-change memory cell. The proposed multi-physics model, which describes the electrical, the thermal, and the phase ...change behavior of the memory cell, can be implemented in a finite-element simulator, with no need for any external algorithm to compute the phase evolution. The goal of this work is to determine, from a macroscopic point of view, the morphological evolution of the phase distribution during the programming pulses. This is useful to investigate the programming conditions that lead, for example, to a series-type or to a parallel-type phase distribution. The proposed model has been validated by comparing the simulated and the experimental SET to RESET programming curve. Finally, the model allowed us to evaluate the different phase distributions obtained after the same programming pulse when starting from different initial RESET conditions.
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