We examine the transfer of graphene grown by chemical vapor deposition (CVD) with polymer scaffolds of poly(methyl methacrylate) (PMMA), poly(lactic acid) (PLA), poly(phthalaldehyde) (PPA), and ...poly(bisphenol A carbonate) (PC). We find that optimally reactive PC scaffolds provide the cleanest graphene transfers without any annealing, after extensive comparison with optical microscopy, x-ray photoelectron spectroscopy, atomic force microscopy, and scanning tunneling microscopy. Comparatively, films transferred with PLA, PPA, PMMA PC, and PMMA have a two-fold higher roughness and a five-fold higher chemical doping. Using PC scaffolds, we demonstrate the clean transfer of CVD multilayer graphene, fluorinated graphene, and hexagonal boron nitride. Our annealing free, PC transfers enable the use of atomically-clean nanomaterials in biomolecule encapsulation and flexible electronic applications.
We analyze the optical, chemical, and electrical properties of chemical vapor deposition (CVD) grown hexagonal boron nitride (h-BN) using the precursor ammonia-borane (H3N–BH3) as a function of Ar/H2 ...background pressure (P TOT). Films grown at P TOT ≤ 2.0 Torr are uniform in thickness, highly crystalline, and consist solely of h-BN. At larger P TOT, with constant precursor flow, the growth rate increases, but the resulting h-BN is more amorphous, disordered, and sp3-bonded. We attribute these changes in h-BN grown at high pressure to incomplete thermolysis of the H3N–BH3 precursor from a passivated Cu catalyst. A similar increase in h-BN growth rate and amorphization is observed even at low P TOT if the H3N–BH3 partial pressure is initially greater than the background pressure P TOT at the beginning of growth. h-BN growth using the H3N–BH3 precursor reproducibly can give large-area, crystalline h-BN thin films, provided that the total pressure is under 2.0 Torr and the precursor flux is well-controlled.
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The high-frequency performance of transistors is usually assessed by speed and gain figures of merit, such as the maximum oscillation frequency f
, cutoff frequency f
, ratio f
/f
, forward ...transmission coefficient S
, and open-circuit voltage gain A
. All these figures of merit must be as large as possible for transistors to be useful in practical electronics applications. Here we demonstrate high-performance graphene field-effect transistors (GFETs) with a thin AlOx gate dielectric which outperform previous state-of-the-art GFETs: we obtained f
/f
> 3, A
> 30 dB, and S
= 12.5 dB (at 10 MHz and depending on the transistor geometry) from S-parameter measurements. A dc characterization of GFETs in ambient conditions reveals good current saturation and relatively large transconductance ~600 S/m. The realized GFETs offer the prospect of using graphene in a much wider range of electronic applications which require substantial gain.
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A central issue of nanoelectronics concerns their fundamental scaling limits, that is, the smallest and most energy-efficient devices that can function reliably. Unlike charge-based electronics that ...are prone to leakage at nanoscale dimensions, memory devices based on phase change materials (PCMs) are more scalable, storing digital information as the crystalline or amorphous state of a material. Here, we describe a novel approach to self-align PCM nanowires with individual carbon nanotube (CNT) electrodes for the first time. The highly scaled and spatially confined memory devices approach the ultimate scaling limits of PCM technology, achieving ultralow programming currents (∼0.1 μA set, ∼1.6 μA reset), outstanding on/off ratios (∼103), and improved endurance and stability at few-nanometer bit dimensions. In addition, the powerful yet simple nanofabrication approach described here can enable confining and probing many other nanoscale and molecular devices self-aligned with CNT electrodes.
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We measure top-gated graphene field-effect transistors (GFETs) with nanosecond-range pulsed gate and drain voltages. Due to high-κ dielectric or graphene imperfections, the drain current decreases by ...~10% over timescales of ~10 μs, consistent with charge trapping mechanisms. The pulsed operation leads to hysteresis-free I-V characteristics that are studied with pulses as short as 75 and 150 ns at the drain and gate, respectively. The pulsed operation enables reliable extraction of GFET intrinsic transconductance and mobility values independent of sweep direction, which are up to a factor of two higher than those obtained from simple dc characterization. We also observe drain-bias-induced charge trapping effects at lateral fields greater than 0.1 V/μm. In addition, using modeling and capacitance-voltage measurements, we extract trap densities up to 1012 cm -2 in the top-gate dielectric (here Al 2 O 3 ). This study illustrates important timeand field-dependent imperfections of top-gated GFETs with high-κ dielectrics, which must be carefully considered for future developments of this technology.
Contact resistance is one of the main factors limiting performance of short-channel graphene field-effect transistors (GFETs), preventing their use in low-voltage applications. Here we investigated ...the contact resistance between graphene grown by chemical vapor deposition (CVD) and different metals, and found that etching holes in graphene below the contacts consistently reduced the contact resistance, down to 23 Ω⋅μm with Au contacts. This low contact resistance was obtained at the Dirac point of graphene, in contrast to previous studies where the lowest contact resistance was obtained at the highest carrier density in graphene (here 200 Ω⋅μm was obtained under such conditions). The 'holey' Au contacts were implemented in GFETs which exhibited an average transconductance of 940 S m−1 at a drain bias of only 0.8 V and gate length of 500 nm, which out-perform GFETs with conventional Au contacts.
The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite ...extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.
The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite ...extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.
The scaling of graphene sub-micron integrated circuits was demonstrated by fabricating and characterizing graphene ring oscillators of different gate lengths, exhibiting the highest oscillation frequency of 4.3 GHz obtained in any strictly low-dimensional material to date.
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