Search results Chang, Junjun

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371.	Maximizing ESD design window by optimizing gate bias for cascoded drivers in 45nm and beyond SOI technologies Mitra, S; Gauthier, R; Shunhua Chang ... Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010, 2010-Oct. Conference Proceeding In advanced SOI technologies, the bottom gate voltage plays an important role in achieving the maximum trigger voltage Vt1 of the cascoded drivers. A comparable MOSFET and BJT current handling is ...	Full text Available for: IJS, NUK, UL, UM
372.	Predictive full circuit ESD simulation and analysis using extended ESD compact models: Methodology and tool implementation Junjun Li; Gauthier, R; Joshi, A ... Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010, 2010-Oct. Conference Proceeding We present a new ESD compact modeling methodology using Verilog-A to enable predictive full circuit ESD simulation along with supporting hardware and failure analysis results. We also present a new ...	Full text Available for: IJS, NUK, UL, UM
373.	Broad ultra-potent neutralization of SARS-CoV-2 variants by monoclonal antibodies specific to the tip of RBD Paper Open access	Full text PDF

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