Recent applications require vertical chip stacking to increase the performance of many devices without the need of advanced node components. Image sensors and vision systems will embed more and more ...smart functions, for instance, image processing, object recognition, and movement detection. In this perspective, the combination of Cu-to-Cu direct hybrid bonding technology with Through-Silicon-Via (TSV) will allow 3D interconnection between pixels and the associated computing and memory structures, each function fabricated on a separate wafer. Wafer-to-wafer hybrid bonding was achieved with multi-pitch design—1–4 μm—of single levels of Cu damascene patterned on 300 mm silicon substrates. Defect-free bonding, as far as the extreme edge of the wafer, was demonstrated on a stack with three wafers. Middle wafers thinning was done with grinding only and with a thickness uniformity (TTV) <2 μm to an ultimate thinning as low as 3 μm. Alignment performance was characterized by post-bonding for two superposed hybrid bonding interfaces. In our set of wafers, modeling the alignment with translation, rotation, and scaling components enables us to optimize the residuals down to 3σ < 100 nm. A process flow of thin TSV with a fine pitch of 2 μm for high-density vertical interconnect through a three-wafer stack was developed. Via-last TSV architecture was adopted with 1 μm TSV diameter and 10 μm thickness. Lithography, etching solutions, Ti/TiN barrier deposition, and void-free Cu filling solutions were demonstrated. TSV cross sections after CMP and connections with top and bottom Cu damascene lines show good profile control. Process developments are matured and can be reliably used in the fabrication of an electrical test vehicle including vertical interconnects associating multi-wafers stacking with a hybrid bonding process and high-density thin TSV applicable to low pitches (<5 μm).
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EMUNI, FIS, FZAB, GEOZS, GIS, IJS, IMTLJ, KILJ, KISLJ, MFDPS, NLZOH, NUK, OILJ, PNG, SAZU, SBCE, SBJE, SBMB, SBNM, UKNU, UL, UM, UPUK, VKSCE, ZAGLJ
Future many cores, either for high performance computing or for embedded applications, are facing the power wall, and cannot be scaled up using only the reduction of technology nodes; 3D integration, ...using through silicon via (TSV) as an advanced packaging technology, allows further system integration, while reducing the power dissipation devoted to system-level communication. In this paper, we present a 3D modular and scalable network-on-chip (NoC) architecture implemented using robust asynchronous logic. The 3DNOC circuit targets a Telecom long-term evolution application; it is composed of two die layers, fabricated in 65 nm technology using TSV middle aspect ratio 1:8, and integrates ESD protection, a 3D design-for-test, and a fault tolerant scheme. The 3D links achieve 0.66 pJ/b energy consumption and 326 Mb/s data rate per pin for the parallel link. Thin die effect is demonstrated by thermal analysis and measurements, as well as the dynamic self-adaptation of the 3D link performances with 3D thermal conditions. Finally, the scalability of the 3DNOC circuit, in terms of power delivery network and thermal dissipation, is demonstrated by using simulations up to a 3D stack of eight die layers.
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•Innovative and realistic 4-port test structures for high wide frequency range characterizations.•Extraction of noise coupling between TSVs and wells in a CMOS 65nm technology node up ...to 40GHz.•Variations in TSV to MOS-wells coupling factors according to polarization is due to p-n junctions.•Physical model built to explain the changes in coupling factor.•Comparison of sensitivity of MOS wells to coupling with TSV.
3D technology (TSVs, RDL, copper pillars) is gaining more and more interest. The functionalities and performances of the Wide I/O prototype (memory on logic 3D IC), developed by ST, ST-Ericson and CEA-LETI, was fully demonstrated. 3D process is mature enough to address next applications such as radiofrequency, analogic, and photonics. Nevertheless new challenges appear when 3D technology and these applications meet together. Particularly the parasitic electrical coupling of the TSV with active devices is a matter of interest and is investigated in this paper.
Considering that the TSV will be a connection for several applications, characterized by a wide frequency domain, the signal transmission could generate substrate noise impacting MOS circuit operations. Noise coupling between TSV and active areas has to be characterized on a wide frequency range. The extraction of this coupling factor in the complex 3D circuit environment represents the bigger challenge of this study.
An original strategy is proposed to investigate the coupling between TSVs and the complex MOS structure, consisting in splitting up the MOS into elementary wells with adequate doping conditions. It entailed innovative test structure design and definition of characterization method with RF and DC sources. The TSV under test is near different MOS wells and the noise coupling transfer factors were measured from 10MHz to 40GHz. They exhibit wide variations, increasing with frequency, from minimum −55dB to maximum −25dB. Variations according to the well implant and its applied polarization is also observed. It is explained by the presence of p-n junctions which is in agreement with an equivalent electrical model of structure.
The sensitivity to substrate noise of PMOS and NMOS wells, standing for drain, source and bulk plug, were characterized and compared. TSV coupling with PMOS device is expected to be more critical than with NMOS. P+ plug is shown to be an efficient solution for substrate noise reduction.
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GEOZS, IJS, IMTLJ, KILJ, KISLJ, NUK, OILJ, PNG, SAZU, SBCE, SBJE, UL, UM, UPCLJ, UPUK
Amongst the cooling solutions proposed to mitigate heat hazard effects in microelectronics, heat spreaders seem to be one of the most suitable when thickness and space constraints are considered. ...This work proposes the use of graphite-based materials as heat spreaders for thermal management of flipchip configurations. Experimental tests and numerical simulations show a significant improvement in the thermal dissipation capabilities of the stack when adding this layer. An additional configuration with a copper heat sink added on top of the heat spreader is also studied. Results indicate a significant reduction of the peak temperature for an integrated graphite heat spreader and a reduction of the average chip temperature if the heat spreader is linked to a copper heat sink. Experimental results are then analyzed by retrosimulation and the thermal path is investigated with or without heatspreader.
3D Stacked Image sensor is the stacking of a Back-Side Illuminated (BSI) CMOS Image Sensor on a logic die. It enables compact size, higher performances and additional functionalities compared to ...standard BSI sensors. The highest footprint reduction is obtained with 3D hybrid bonding with metal interconnects between top and bottom tiers. Hybrid bonding process with oxide / copper direct bonding allows the highest scalability of interconnect pitch. In this study we present the morphological and electrical characterizations of a test vehicle. The hybrid bonding of wafers from two different technology nodes is performed using a dual damascene integration for the hybrid bonding level. The main parameters to assess the bonding interface quality are analyzed such as the influence of the pad design, the impact of reworkability and wafer -- to-wafer overlays. The process robustness is studied through reliability tests and electromigration measurements.
Future many cores, either for high performance computing or for embedded applications, are facing the powerwall, and cannot be scaled up using only the reduction of technology nodes; 3D integration, ...using through siliconvia (TSV) as an advanced packaging technology, allows further system integration, while reducing the power dissipationdevoted to system-level communication. In this paper, we present a 3D modular and scalable network-on-chip (NoC) architecture implemented using robust asynchronous logic. The 3DNOC circuit targets a Telecom long-term evolution application; it is composed of two die layers, fabricated in 65 nm technology using TSV middle aspect ratio 1:8, and integrates ESD protection, a 3D design-for-test, and a fault tolerant scheme. The 3D links achieve 0.66 pJ/b energy consumption and 326 Mb/s data rate per pin for the parallel link. Thin die effect is demonstrated by thermal analysis and measurements, as well as the dynamic self-adaptation of the 3D link performances with 3D thermal conditions. Finally, the scalability of the 3DNOC circuit, interms of power delivery network and thermal dissipation, is demonstrated by using simulations up to a 3D stack of eightdie layers.
In the context of high performance computing (HPC), energy efficiency and computing density are key for targeting exascale architectures. Close integration of chiplets, active interposer and field ...programmable gate arrays (FPGA) paves the way for dense, efficient and modular compute nodes. In this paper, we detail the ExaNoDe multi-chip-module (MCM) combining the integration of a substrate, an active interposer, some chiplets and bare dice. The reported MCM demonstrates that the multi-level integration flow enables tight integration of hardware accelerators in a heterogeneous HPC compute node.
3D TSV integration enables scalable manycore architectures, however they require advanced cache coherence features to enable simple programming models. We propose TSARLET, a general purpose 16-core ...computing fabric targeting 3D TSV integration with a fully scalable cache coherent memory architecture, using distributed L2-caches, and adaptive fault tolerant L3-caches. Implemented in 28nm UTBB FDSOI technology, the circuit operates up to 1.15 GHz using adaptive clocking and provides 29 Gops/W in the 0.5-1.3V supply range. The chip's performance is demonstrated using an image filter application and an OpenMP based Convolutional Neural Network (CNN) on Linux.
Specific surfaces allowing Ultra-High Vacuum (UHV) investigations are required for the successful development of atomic nanostructures. Surface contamination, atomic roughness and defects density ...must be controlled in order to ensure the reliability of advanced UHV experiments. Surface preparation is a key parameter and is usually conducted in-situ in the UHV chamber. However the surface preparation requires a complex protocol. A microelectronic clean room environment enables the particles density control and enables 200mm wafer scale developments, especially Si(001)-(2x1):H surface reconstruction. However, this passivated surface is reactive and can be easily deteriorated, particularly during transportation. Consequently, a nanopackaging solution is proposed in order to provide a preserving environment for transportation. The nanopackaging process consists in the direct bonding of two passivated silicon surfaces, and is followed by a wafer dicing step into 1cm2 dies. Samples can be stored, shipped and in-situ opened without additional treatment. Furthermore, these samples can provide a reliable surface onto which molecular grafting can be accomplished. The fabrication modules and the associated characterization results will be described as well as atomic nanostructure manipulations and especially the grafting of a self-assembled monolayer using supercritical carbon dioxide as a medium.
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GEOZS, IJS, IMTLJ, KILJ, KISLJ, NLZOH, NUK, OILJ, PNG, SAZU, SBCE, SBJE, UILJ, UL, UM, UPCLJ, UPUK, ZAGLJ, ZRSKP
From low density 3D integrations embedding Via Last Through Silicon Vias (TSV) to high densities hybrid bonding or 3D VSLI CoolCubeTM solutions, a multitude of new product opportunities is now ...envisioned. An overview of existing emerging 3D integrations is provided covering Image sensors, Photonics, MEMS, Wide I/O memories and Silicon Interposers for advanced logics. Associated key challenges and developments are highlighted focusing on 3D platform performance assessment.
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