This paper presents a 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity, operating speed, and power efficiency. The implemented ADC employs an improved ...SHA with parasitic optimized bootstrapped switches to achieve high sampling linearity over a wide input frequency range. It also explores a dedicated foreground calibration to correct the capacitor mismatches and the gain error of residue amplifier, where a novel configuration scheme with little cost for analog front-end is developed. Moreover, a partial non-overlapping clock scheme associated with a high-speed reference buffer and fast comparators is proposed to maximize the residue settling time. The implemented ADC is measured under different input frequencies with a sampling rate of 250 MS/s and it consumes 300 mW from a 1.8 V supply. For 30 MHz input, the measured SFDR and SNDR of the ADC is 94.7 dB and 68.5 dB, which can remain over 84.3 dB and 65.4 dB for up to 400 MHz. The measured DNL and INL after calibration are optimized to 0.15 LSB and 1.00 LSB, respectively, while the Walden FOM at Nyquist frequency is 0.57 pJ/step.
This paper presents a 40-Gb/s transmitter (TX) and receiver (RX) chipset for chip-to-chip communications in a 65-nm CMOS process. The TX implements a quarter-rate multi-multiplexer (MUX)-based ...four-tap feed-forward equalizer (FFE), where a charge-sharing-effect elimination technique is introduced into the 4:1 MUX to optimize its jitter performance and power efficiency. The RX employs a two-stage continuous-time linear equalizer as the analog front end and integrates a low-cost sign-based zero-forcing engine relying on edge-data correlation to automatically adjust the tap weights of the TX-FFE. By embedding low-pass filters with an adaptively adjusting bandwidth into the data-sampling path and adopting high-linearity compensating phase interpolators, the clock data recovery achieves both high jitter tolerance and low jitter generation. The fabricated TX and RX chipset delivers 40-Gb/s PRBS data at BER <; 10-12 over a channel with >16-dB loss at half-baud frequency, while consuming a total power of 370 mW.
A 14-bit 250MS/s low power pipeline analog-to-digital converter (ADC) implemented in a 0.18μιη CMOS process is presented in this paper. A SHA-less 3.5-bit front-end is adopted to achieve low power ...design. An aperture error eliminating technique and flash ADC optimization design techniques such as capacitor splitting, interpolation, and offset calibration, are both used to achieve wideband input even for the front-end with resolution up to 3.5-bit. The post simulation results show this ADC achieves an SNR of 74.6 dB, an SNDR of 74.4 dB and an SFDR of 87.1 dB with a 70MHz input signal, while maintaining an SNR > 72.5 dB and an SFDR > 77.4 dB up to 900MHz input signals. The ADC consumes 120mW from a 1.8 V supply.
An ultrahigh-frequency RF identification system, consisting of a fully integrated tag and a special reader, has been developed for short-range and harsh size requirement applications. The system is ...fabricated in the standard 0.18-μm CMOS process. The whole tag chip with an antenna, an analog front end, a baseband, and memory takes up an area of 0.36 mm 2 , which is smaller than other reported tags with an on-chip antenna (OCA) using the standard CMOS process. A self-defined protocol is proposed to reduce the power consumption and minimize the size of the tag. A specialized system-on-a-chip reader system, consisting of RF transceiver, digital baseband, MCU, and host interface, supports both the self-defined and International Standards Organization 18000-6 C protocols. Its power consumption is about 500 mW, which is much lower than other reported readers considering the transmission power. Measurement results show that the system's reading range is 2 mm with a 20-dBm reader output power. In addition, it has been verified that the data stored in the OCA tag embedded in a pearl can be successfully read out. With an inductive antenna printed on a paper substrate around the OCA tag, the reading range can be extended from several centimeters to meters depending on the shape and size of the inductive antenna.
Abstract
Insufficient and imbalanced samples pose a significant challenge in bearing fault diagnosis, leading to low diagnosis accuracy. However, the fault characteristics of vibration signals are ...weak and difficult to extract when faults occur in the early stage. This paper proposes an effective fault diagnosis method that addresses small and imbalanced sample problems under noise interference. First, the number of faulty samples in the form of 1D signals is increased mainly by the sliding split sampling method. The preprocessed data are used to create 2D time–frequency diagrams using the continuous wavelet transform (CWT), which can extract effective features to improve the data quality. Subsequently, the minority samples are oversampled by combining synthetic minority oversampling technique to realize time–frequency conversion augmented oversampling. Moreover, the clustering method and random undersampling method are introduced to prevent the overfitting and underfitting problems respectively. Then, we propose a hybrid attention mechanism to enhance the extraction of effective feature information. This combination, integrating CWT with a multicolumn modified deep residual network, effectively extracts fault characteristics and suppresses noise effects. The experimental results demonstrate the effectiveness of the proposed method by comparison with other advanced methods using two case studies of bearing datasets.
This paper presents a low-power transceiver with a reconfigurable sliding-IF (intermediate frequency) architecture targeted for wireless body area networks hubs covering 400 MHz and 2.4 GHz bands. By ...using this architecture, a 1608-1988 MHz PLL synthesizer with only 21% tuning range can fully cover all the available bands around 400 MHz and 2.4 GHz as defined by IEEE 802.15.6 NB (narrow band) and ZigBee. The dual-band transceiver has been designed in 0.18 μm CMOS process. The design consists of a receiver with a wideband front-end and a reconfigurable amplifier-mixer, a transmitter with a reconfigurable two stage full quadrature mixer, a ΣΔ fractional-N PLL and some auxiliary circuits. The measurement result has demonstrated that the proposed transceiver can satisfy the dual-band requirements with comparable or even better performance in noise, receiver sensitivity and power consumption compared to previously-reported transceivers for only a single band.
A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and ...capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.
This paper presents a low-power 2-channel 12-bit 2GS/S time-interleaved pipelined-SAR ADC in 28nm CMOS process. The design adopts SHA-less front-end, capacitor sharing between stages, current-reused ...and ping-pong operated MDAC amplifier, and hybrid reference buffer to reduce power consumption and optimize performance. Pre-layout simulation with noise shows that the proposed ADC achieves SNDR and SFDR of 64.1dB and 69.5dB respectively at Nyquist frequency. The effective resolution bandwidth is extended to 3.2GHz. The ADC consumes only 50mW, in which 30mW is dissipated by the wide-band input buffer. At Nyquist frequency, the proposed ADC achieves a Waiden FOM of 19fJ/conv.-step.
This brief presents a 14-bit 4 GS/s time-interleaving ADC design using two interleaved sub-ADCs. The sub-ADC achieves 2 GS/s conversion rate in 28 nm CMOS technology and uses pipelined structure to ...have high resolution at the same time. In the adopted sample-and-hold amplifier-less (SHA-less) pipeline, a comparator-based correction method is proposed to solve the associated aperture error in the frontend stage where input is sampled at the latch node. By tunning the path bandwidth, rather than using delay line in comparator clock path, the output spreading related to aperture error is reduced by the proposed tunning method to offset-limited level up to 4 GHz input frequency. The modified reference buffer in the ADC reuses the existing transconductance and improves its power efficiency when driving the pipeline stages. Buffers and digital calibrations are implemented on-chip to help wideband high-speed operation and to correct non-idealities in analog circuits. The fabricated ADC chip achieves 59.7 dB SNDR, 60.3 dB SNR and 69.3 dBc SFDR at 1.95 GHz input frequency. The input bandwidth is above 5 GHz. ADC power consumption is 782 mW, resulting in 247.8 fJ/conv.-step <inline-formula> <tex-math notation="LaTeX">{\rm FoM_{W}} </tex-math></inline-formula> and 153.7 dB FoMS.
A novel low-power DC offset calibration (DCOC) method independent of intermediate frequency (IF) gain for zero-IF receiver applications has been reported. The conventional analog DCOC method consumes ...greater power and affects the performance of the receiver. The conventional mixed-signal method requires enhanced memory to store the calibration results at different receiver gains as the DC offset is relative to the radio frequency (RF) and IF gain. A novel algorithm is presented to make the DCOC process independent of IF gain, which significantly reduces the memory area. With the proposed circuit, the receiver calibrates only once so settle-time and power consumption of the IF circuit is lowered. A DCOC circuit with the proposed method is manufactured in 0.18 μm CMOS technology that drains nearly 0 mA equivalent current from a 1.8 V power supply.
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