A CMOS sensor chip for charged particle detection has been developed and submitted for fabrication in a 0.18 μm Quadruple-Well (N&P-Wells, Deep N&P-Wells) CMOS Image Sensor (CIS) process. Improvement ...of the radiation hardness, the power dissipation and the readout speed of the mainstream CMOS sensors is expected with the exploration of this process. In order to ensure better charge collection and neutron tolerance, wafers with high-resistivity epitaxial layer have been chosen. In this paper a digital CMOS sensor prototype developed in order to validate the key analog blocks (from sensing element to 1-bit digital conversion) of a binary Monolithic Active Pixel Sensor (MAPS) in this process will be presented. The digital sensor prototype comprises four different sub-arrays of 20 μm pitch 64 × 32 pixels, 128 column-level auto-zeroed discriminators, a sequencer and an output digital multiplexer. Laboratory tests results including the charge-to-voltage conversion factor, the charge collection efficiency, the temporal noise and the fixed-pattern noise are presented in details. Some irradiation results will also be given.
CMOS pixel sensors are foreseen to equip the vertex detector (called PXL) of the upgraded inner tracking system of the STAR experiment at RHIC. The sensors (called ULTIMATE) are being designed and ...their architecture is being optimized for the PXL specifications, extrapolating from the MIMOSA-26 sensor realized for the EUDET beam telescope.
The paper gives an overview of the ULTIMATE sensor specifications and of the adaptation of its forerunner, MIMOSA-26, to the PXL specifications.
One of the main changes between MIMOSA-26 and ULTIMATE is the use of a high resistivity epitaxial layer. Recent performance assessments obtained with MIMOSA-26 sensors manufactured on such an epitaxial layer are presented, as well as results of beam tests obtained with a prototype probing improved versions of the MIMOSA-26 pixel design. They show drastic improvements of the pixel signal-to-noise ratio and of the sensor radiation tolerance with respect to the performances achieved with a standard, i.e. low resistivity, layer.
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A 48 x 64 pixels prototype CMOS pixel sensor (CPS) integrated with 4-bit column-level, self triggered ADCs for the outer layers of the ILD vertex detector (VTX) was developed and fabricated in a 0.35 ...mu m CMOS process with a pixel pitch of 35 mu m. The pixel concept combines inpixel amplification with a correlated double sampling (CDS) operation. The ADCs accommodating the pixel read out in a rolling shutter mode complete the conversion by performing a multi-bit/step approximation. The design was optimised for power saving at sampling frequency. The prototype sensor is currently at the stage of being started testing and evaluation. So what is described is based on post simulation results rather than test data. This 4-bit ADC dissipates, at a 3-V supply and 6.25-MS/s sampling rate, 486 mu W in its inactive mode, which is by far the most frequent. This value rises to 714 mu W in case of the active mode. Its footprint amounts to 35 x 545 mu m super(2).
A low-noise multi-channel charge-sensitive preamplifier (CSA), designed in AMS 0.35 μm CMOS process, is presented for both its theoretical analysis and its CAD simulation. It is foreseen to be used ...as front end readout electronics of Avalanche Photo Diodes (APD) dedicated to a small animal Positron Emission Tomography (PET) system. The CSA reads charge signals (10 bits dynamic range) from an APD array having 10 pF of capacitance per pixel. A linearized degenerated differential pair which ensures high linearity in all dynamical range is used as the high feedback resistor for preventing pile up of signals. The designed CSA has the capability of compensating automatically up to 40 nA leakage current from detector. An equivalent input noise charge of 330 e- rms has been obtained from simulation for a 10 pF detector capacitance and 40 nA leakage current.
This paper represents the design of a low-noise, wide band multi-channel readout integrated circuit (IC) used as front end readout electronics of avalanche photo diodes (APD) dedicated to a small ...animal positron emission tomography (PET) system. The first ten-channel prototype chip (APD-Chip) of the analog parts has been designed and fabricated in a 0.35 μm CMOS process. Every channel of the APD_Chip includes a charge-sensitive preamplifier (CSA), a CR-(RC) 2 shaper, and an analog buffer. In a channel, the CSA reads charge signals (10 bits dynamic range) from an APD array having 10 pF of capacitance per pixel. A linearized degenerated differential pair which ensures high linearity in all dynamical range is used as the high feedback resistor for preventing pile up of signals. The designed CSA has the capability of compensating automatically up to 200 nA leakage current from the detector. The CR-(RC) 2 shaper filters and shapes the output signal of the CSA. An equivalent input noise charge obtained from test is 275 e - + 10 e - /pF. In this paper the prototype is presented for both its theoretical analysis and its test results.
This paper presents the design of a low-noise multi-channel front-end readout chip integrated with a high-resolution TDC. It is foreseen to be used as front-end readout electronics of Avalanche Photo ...Diodes (APD) dedicated to a small animal Positron Emission Tomography (PET) system. The architecture of the chip is reported. Two prototype chips, a ten-channel front-end chip and a three-channel high-resolution TDC, have been designed in AMS 0.35 μm CMOS technology. A low-noise charge-sensitive amplifier (CSA) and a shaper are integrated in each channel of the front-end chip. The proposed CSA performs a compensation of the 40 nA dark current coming from the detector. An equivalent input noise charge of 275 e - + 10 e - /pF (rms) has been obtained from test. The TDC chip is based on coarse-fine two-level conversion scheme. In the coarse conversion, a 10-bit counter is employed to achieve a wide range. Meanwhile, the time interpolation using an array of delay-locked loops is proposed for fine conversion. The measured time range is 10 μs. The bin size has been achieved from 71 ps to 142 ps with a reference clock from 100 MHz to 50 MHz.
Development of monolithic active pixel sensors for charged particle tracking Deptuch, G; Claus, G; Colledani, C ...
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment,
09/2003, Volume:
511, Issue:
1
Journal Article, Conference Proceeding
Peer reviewed
Monolithic active pixel sensors introduce a detection technique, where the active detecting element is a thin, moderately doped, and undepleted silicon layer and the readout electronics is implanted ...on top of it. The built-in potential, resulting from differences in doping, screens both parts, as well as it confines the charge diffusing to the readout electrodes. The R&D was triggered by the increasing need of high performance flavour identification capabilities that should be provided by future vertex detectors. The viability of the technology and its high tracking performances were demonstrated with small-scale prototypes, made of small arrays of a few thousands of pixels and more recently with a first prototype of a serviceable size of one million pixels. This paper summarizes results from tests performed with relativistic charged particles on prototypes essentially fabricated with a classical 3-transistor pixel configuration. Within the last year, two novel ideas optimising the pixel design for a vertex detector have been developed. They are presented with test results assessing their suitability.
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With the purpose of measuring simultaneously the proton and electron environmentusing a single sensitive device, we propose a CMOS pixel sensor featuring a 10 mm2 sensitivearea, counting capability ...up to 10 super(7)/cm super(2)/s and with a minimal error due to pileup of two closeparticle impacts on the matrix. The proposed architecture includes a 64 x 64 square pixel matrixwith 50 mu m pitch size, 64 column level 3-bit ADCs to provide an appropriate energy resolution, andan embedded digital logic that directly calculates the particle properties from the hit informationprovided by the pixels. To validate experimentally the expected performance within the year 2012, a first prototype has been designed and fabricated in a 0.35 mu m process without the integrateddigital processing part. The device simulation and design architecture are presented.
The PLUME (Pixelated Ladder with Ultra-Low Material Embedding) Collaboration is developing ultra-light ladders for the vertex detector for a future linear collider. The double-sided ladder will ...integrate the sensors, readout infrastructure and mechanical supports with the aim of total material budget of 0.3% of radiation length. The requirement of as light as possible construction is driven by physics, in particular by measurements requiring determination of the quark charge sign. The first prototype ladders were prepared and tested in the beam. The alignment issues for the ladders will be tested within the AIDA (Advanced European Infrastructures for Detectors at Accelerators) EU FP7 project.
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10.
Improved radiation tolerance of MAPS using a depleted epitaxial layer Dorokhov, A.; Bertolone, G.; Baudot, J. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
12/2010, Volume:
624, Issue:
2
Journal Article
Peer reviewed
Tracking performance of Monolithic Active Pixel Sensors (MAPS) developed at IPHC (Turchetta, et al., 2001)
1 have been extensively studied (Winter, et al., 2001; Gornushkin, et al., 2002)
2,3. ...Numerous sensor prototypes, called MIMOSA,
1
1
Standing for Minimum Ionising particle MOS Active pixel sensors.
were fabricated and tested since 1999 in order to optimise the charge collection efficiency and power dissipation, to minimise the noise and to increase the readout speed.
The radiation tolerance was also investigated. The highest fluence tolerable for a
10
μ
m
pitch device was found to be
∼
10
13
n
eq
/
cm
2
, while it was only
2
×
10
12
n
eq
/
cm
2
for a
20
μ
m
pitch device. The purpose of this paper is to show that the tolerance to non-ionising radiation may be extended up to
O(10
14) n
eq/cm
2. This goal relies on a fabrication process featuring a
15
μ
m
thin, high resistivity (
∼
1
k
Ω
cm
) epitaxial layer. A sensor prototype (MIMOSA-25) was fabricated in this process to explore its detection performance. The depletion depth of the epitaxial layer at standard CMOS voltages (
<
5
V
) is similar to the layer thickness. Measurements with m.i.p.s
2
2
Standing for minimum ionising particle.
show that the charge collected in the seed pixel is at least twice larger for the depleted epitaxial layer than for the undepleted one, translating into a signal-to-noise ratio (SNR) of
∼
50
. Tests after irradiation have shown that this excellent performance is maintained up to the highest fluence considered (
3
×
10
13
n
eq
/
cm
2
)
, making evidence of a significant extension of the radiation tolerance limits of MAPS.
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