A robust FinFET silicon-controlled rectifier (SCR) LDMOS ESD protection device is developed. Replacing the drain contact implant to the P+ implant from N+ implant creates an SCR inside the LDMOS and ...when the N+ contact is removed a Schottky SCR LDMOS is created. The ESD performance of the baseline FinFET LDMOS is Zero, while that of the SCR LDMOS is 9.2 mA/<inline-formula> <tex-math notation="LaTeX">\mu {\mathrm{ m}} </tex-math></inline-formula> and Schottky SCR is 4.6 mA/<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> respectively.
Physics of correlation between standard ESD testing and transmission line pulse test results on semiconductor devices using a simple resistor (R) inductor (L) capacitor (C) circuit model approach is ...presented. The correlation is not a constant factor, however, it can be used to evaluate the time to failure for the device during the human-body model event and is attributed to the time to induce the thermal runaway of the device during the electrostatic-discharge event.
For the first time, the influence of fast pulse induced skin effect on the current distribution inside the grounded-gate NMOS (GGNMOS) is reported. The skin effect results in the current crowding at ...the finger edges of the GGNMOS, leading to the high photoemission and high substrate potential at those regions. This report comprehensively explains some of the decades-old unexplained physical phenomena.
From the Joules-Atherton (J-A) model, the sign of magnetization energy loss due to hysteresis at the positive-going magnetic field H is opposite to that at the negative-going magnetic field H, which ...is + 1 if dH/dt>0 and is - 1 if dH/dt<0. This implies that an inductor has the different inductances at the current ramp-up time due to dH/dt>0 and ramp-down time due to dH/dt<0. However, this phenomenon is never reported until now. In this paper, the inductance of an inductor is found which is larger than the intrinsic inductance at the current ramp-up time (t up )and smaller than the intrinsic inductance at the current ramp-down time (t dn )for a boost converter during the continuous conduction mode voltage converter. Moreover, hysteresis also makes the classical model of the voltage conversion ratio for boost converter design, V OUT /V IN = 1/(1-D), invalid since D (t up /T) is not a constant caused by the t up and t dn varied with the output current of boost converter, where t up +t dn =T, The hysteresis model aids designers in estimating the behavior of inductor current variations more accurately, without having to wait for chip manufacturing and measurement to reveal the actual behavior.
A novel high electrostatic discharge (ESD), robust fully salicided 5-V integrated CMOS power MOSFET design is developed and demonstrated without the use of conventional salicide blocking ballast ...resistor. This scheme builds the ballast resistors on the top of the source and drain, without any increase in silicon footprint unlike prior methods, while maintaining standard transistor parametric performance.
We propose and implement a new low-voltage triggering silicon-controlled rectifier (SCR) embedded in the guard rings of a lateral diffused MOS (LDMOS) transistor. According to the reduced ...surface-field principle, the breakdown voltage is almost proportional to the lateral distance of the high-voltage n-well 1. Because its trigger voltage (Vt1) is lower than that of the LDMOS, the proposed SCR protects the LDMOS from electrostatic stress damage, without requiring special processes, trigger devices, trigger circuits, and increasing the device dimension. Therefore, it is expected to realize next-generation small-scale devices.
LATS2 is a member of the LATS tumor suppressor family. It has been implicated in regulation of the cell cycle and apoptosis. Frequent loss of heterozygosity (LOH) of LATS2 has been reported in human ...esophageal cancer. But, the LATS2 gene expression and its regulatory mechanism in esophageal cancer remain unclear. The present study has shown that LATS2 protein expression was mediated by miR-373 at the post-transcriptional level and inversely correlated with miR-373 amounts in esophageal cancer cell lines. Furthermore, we demonstrated that the direct inhibition of LATS2 protein was mediated by miR-373 and manipulated the expression of miR-373 to affect esophageal cancer cells growth. Moreover, this correlation was supported by data collected
ex vivo, in which esophageal cancer tissues from esophageal squamous cell carcinoma (ESCC) patients were analyzed. Finally, by miRNA microarray analysis, four miRNAs including miR-373 were over-expressed in ESCC samples. Our findings reveal that miR-373 would be a potential oncogene and it participates in the carcinogenesis of human esophageal cancer by suppressing LATS2 expression.
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GEOZS, IJS, IMTLJ, KILJ, KISLJ, NUK, OILJ, PNG, SAZU, SBCE, SBJE, UL, UM, UPCLJ, UPUK
Energy handling capability of large-array devices (LADs) is one of the most dominating concerns for the designers that affect the device design and its reliability. In this paper, the improvement of ...the avalanche ruggedness capability by using an optional implantation layer has been investigated the first time for the application of 5-V n-channel large-array MOSFET in a bipolar-CMOS-DMOS (BCD) process. Experimental results with extensive measurements verified that the maximum avalanche current (<inline-formula> <tex-math notation="LaTeX">{I}_{\text {AV}} </tex-math></inline-formula>) achieved from the modified device is enhanced by more than twice. Moreover, the energy in avalanche single pulse (EAS) capability is improved by more than five times. A significant improvement is noticed in the avalanche safe-operating-area (A-SOA) as compared to the original device, and the failure analysis is discussed in detail. In addition, the impact of an optional implantation layer on the total gate charge (Qg) is also compared for a LAD with a total width of 12<inline-formula> <tex-math notation="LaTeX">000~\mu \text{m} </tex-math></inline-formula>.
This paper investigates the electrostatic discharge (ESD) failure mechanism in the human body model of circular ultrahigh voltage lateral diffused MOS-type devices. Failure occurs due to the current ...crowding effect at the N+ junction edge of the drain adjacent to the field oxide. Instead of a large single N+ diffusion, a novel drain design with small multidiffusions is proposed to eliminate the current crowding and to enhance its ESD performance.
Based on the voltage and current waveforms, the mechanism of the system-level electrostatic-discharge (ESD) induced the voltage fluctuation to the power of integrated circuits (ICs) on system board ...is studied. When a contact discharge ESD test is performed at a connector pin, which is terminated with an I/O pin of an IC, not all the current from the system-level ESD may flow through the IC to the ground of the system board. So, the remaining currents can only flow through the power line of the ICs and the connection wire into the power supply to the ground. The power supply has the feedback and pulsewidth modulation circuits to regulate its output voltage. Therefore, the output current of the power supply will interact with the remnant current from the ICs on system board, resulting in the current flowing through the connection wire in the microelectronics system back and forth. Hence, the power of system board will be pulled up and down by the connection wire based on L·(dI/dt), since it acts as an inductor during the alternating current. With the voltage swinging up and down, the p-n junctions in the power domain seems to be driven into the avalanche breakdown or forwarded to generate a lot of electrons and holes inside the ICs, leading to the latch-up event at the low latch-up immunity region.
