Recent applications require vertical chip stacking to increase the performance of many devices without the need of advanced node components. Image sensors and vision systems will embed more and more ...smart functions, for instance, image processing, object recognition, and movement detection. In this perspective, the combination of Cu-to-Cu direct hybrid bonding technology with Through-Silicon-Via (TSV) will allow 3D interconnection between pixels and the associated computing and memory structures, each function fabricated on a separate wafer. Wafer-to-wafer hybrid bonding was achieved with multi-pitch design—1–4 μm—of single levels of Cu damascene patterned on 300 mm silicon substrates. Defect-free bonding, as far as the extreme edge of the wafer, was demonstrated on a stack with three wafers. Middle wafers thinning was done with grinding only and with a thickness uniformity (TTV) <2 μm to an ultimate thinning as low as 3 μm. Alignment performance was characterized by post-bonding for two superposed hybrid bonding interfaces. In our set of wafers, modeling the alignment with translation, rotation, and scaling components enables us to optimize the residuals down to 3σ < 100 nm. A process flow of thin TSV with a fine pitch of 2 μm for high-density vertical interconnect through a three-wafer stack was developed. Via-last TSV architecture was adopted with 1 μm TSV diameter and 10 μm thickness. Lithography, etching solutions, Ti/TiN barrier deposition, and void-free Cu filling solutions were demonstrated. TSV cross sections after CMP and connections with top and bottom Cu damascene lines show good profile control. Process developments are matured and can be reliably used in the fabrication of an electrical test vehicle including vertical interconnects associating multi-wafers stacking with a hybrid bonding process and high-density thin TSV applicable to low pitches (<5 μm).
Full text
Available for:
EMUNI, FIS, FZAB, GEOZS, GIS, IJS, IMTLJ, KILJ, KISLJ, MFDPS, NLZOH, NUK, OILJ, PNG, SAZU, SBCE, SBJE, SBMB, SBNM, UKNU, UL, UM, UPUK, VKSCE, ZAGLJ
3D integration of wafers stacking is obtained with a GaN-based wafer integrated on Si substrate and CMOS wafer. In this study, after planarization of the incoming wafers prior the bonding, ...wafer-to-wafer hybrid bonding technology was provided with a mirror design of Cu patterns embedded in silica matrix to provide direct 3D links in a face-to-face scheme with a low pitch of 3 \mu\mathrm{m} . Then, 1 \mu\mathrm{m} Cu TSV-last patterned through the SOI substrate of the CMOS wafer with and AlCu routing lines was followed with copper pillars in order to connect the stack to the package. We present morphological and electrical characterizations of a test vehicle including a Cu/SiO2 hybrid bonding interface. Scanning Acoustic Microscopy, FIB-SEM and TEM cross-sections demonstrated both a perfect SiO 2 /SiO 2 bonding as well as an excellent Cu/Cu connection validated with electrical data.
Adhesion energy and bonding wave velocity are key parameters that should be controlled in an industrial direct bonding process because it reports what exactly occurs at the time of the bonding. While ...dynamics of the bonding front has been analytically studied and modelled 1-4, the literature gives not much information about its characterization. This study is then focused on adhesion energy (Ea) and bonding wave velocity (Vo) measurement. After considerations about immediate and stabilized adhesion energy, we will show the dependence between Ea and Vo and we will confirm Rieutord's model 1 for hydrophilic direct bonding. Roughness dependence, plasma pre-treatment, hydrophobic direct bonding and re-bonding will also be discussed.
Direct bonding energy relates to the well-known "strength" or "toughness" of wafer direct bonding interface. It is the energy needed to separate two bonded surfaces. In contrast, adhesion energy is ...the energy available to bring the two surfaces together. Due to hysteretic effects, the two energies may be different and, while the first energy has been largely measured, the second one is the subject of very few papers. In this study, a new phenomenon will be shown in adhesion energy behavior using two silicon wafers. Several partial debondings and rebondings of the same silicon direct bonding structure result in an increase of the bonding wave speed and consequently of the adhesion energy. Using an electrostatic field, it will be shown that this behavior is linked to the electrical states of the bonding interface. This phenomena is not well understood, although it sheds new light on the adhesion mechanism.
This work demonstrates for the first time the 3D sequential integration of CMOS over CMOS with advanced metal line levels (28nm Cu + ULK). The bottom tier consists of a 28nm FDSOI industrial wafer ...with 4 metal lines. A bevel contamination wrap module allows the return of the wafer to Front End Of Line (FEOL) environment required for achieving high performance top FET Si CMOS processing. Additionally the doped poly-Si ground plane introduced enables top FET dynamic back-biasing and effective DC and HF isolation with underlying metal lines. Finally, this 3DSI platform demonstrates functional top, bottom, and 3D ring oscillators as well as a pixel with single exposure flicker-free High Dynamic Range capability obtained thanks to the stacking of an additional circuit over a bottom 3T-pixel.
Copper/oxide hybrid bonding process has been extensively studied these past years as a key enabler for 3D high density application with top and bottom tier interconnection pitch below 10μm. Since ...2015 hybrid bonding process robustness has been confirmed on complete electrical test vehicles 1,2 as well as commercial products 3 integrating copper to copper interconnection pitchs close to 6μm. To our knowledge, no results have been shown today demonstrating sub-1.5μm pitch copper hybrid bonding feasibility.
Current 3D integrated devices based on copper hybrid bonding are only integrating dual-damascene CMOS processes for interconnection.. In this study, we have developed a Titanium/Oxide (Ti/SiO 2 ) ...hybrid bonding technology suitable for 200 mm non-copper technology platforms featuring aluminum back-ends. A combination of material stack, CMP parameters and design rules enabled us to obtain defect-free bond interface across the wafer. Scanning acoustic microscopy, FIB-SEM and TEM cross-sections demonstrated a perfect SiO 2 /SiO 2 bonding as well as excellent Ti/Ti connections for Ti pads as small as 3×3 µm 2 . Moreover, we designed an electrical test vehicle including a Ti/SiO 2 hybrid-bonding interface, with W vias and AlCu metal interconnects. Despite the integration stack, the bonding interface remains defect-free with contact pads ranging from 10×10 µm 2 down to 3×3 µm 2 . The 3D interconnect showed a contact resistance of 1 Ω and a parasitic capacitance of less than 2 fF. Finally, we report on the process reliability by means of thermal cycling and high-temperature storage, which confirmed the robustness of this innovative Ti/SiO 2 fine pitch interconnection.
Die-to-wafer stacking is very promising for the next 3DIC generation since it offers the ability to assemble several dies with small interconnection pitches. This paper proposes an overall ...integration scheme D2W HB process to reinforce its robustness and its economical relevance for microelectronics industry. Firstly, a KGD strategy was developed to be compatible with hybrid bonding. A successful D2W bonding was demonstrated with tested pads. Secondly, the development of the planarization of stacked dies is presented.
Direct wafer bonding of wafers is now well establish. However in many interesting applications, direct bonding of die to wafer can lead to innovative devices. After explaining some specific ...fundamental mechanisms, III/V die to wafer bonding and copper hybrid bonding will be presented for photonic and 3D applications.
The main goal of this work was to develop a low-cost technology based on the convergence of different processes (Powder Injection Molding, Hot Pressing, Spark Plasma Sintering and Ink-jet Printing). ...The objective was to produce high temperature demonstrator (up to 400°C - 752°F). A ceramic material has been chosen for the substrate and optimized for PIM process. Thermal conductivity obtained was less than 4W/m K and 3D complex shape developed. High conductive material properties have been used for heat-sink and produced by PIM process. Thermo electric material developed is based on Skutterudite materials shaped by hot pressing process. For electrical connectors, ink-jet printing process has been evaluated based on Silver material. Two demonstrators have been produced (low/high temperature) and evaluated in real conditions. The objective is to show that the convergence of technologies allows to obtain new functions, and performances for example for waste heat recovery.
