This article introduces a 192-Gb 896-GB/s 12-high stacked third-generation high-bandwidth memory (HBM3 DRAM) with low power consumption and high-reliability traits. New design schemes and features, ...including internal low-voltage signaling, center strobe calibration, through-silicon via (TSV) auto-calibration, a symbol-correcting in-DRAM ECC, and machine-learning-based layout optimization, allow large amounts of data transfers among the vertically stacked base and core dies with limited delay mismatch or SI degradation, as well as reduced power consumption from low-voltage swings. Experimental results confirm 896-GB/s bandwidth operations at 1.0-V voltage conditions with up to 15% improved power efficiency.
In this paper, HBM DRAM with TSV technique is introduced. This paper covers the general TSV feature and techniques such as TSV architecture, TSV reliability, TSV open / short test, and TSV repair. ...And HBM DRAM, representative DRAM product using TSV, is widely presented, especially the use and features.
With the emergence of large-language models (LLM) and generative AI, which require an enormous amount of model parameters, the required memory bandwidth and capacity for high-end systems is on an ...unprecedented increase. To meet this need, we present an extended version of the high-bandwidth memory-3 (HBM3 DRAM), HBM3E, which achieves a 1280GB/s bandwidth with a cube density of 48GB. New design schemes and features, such as all-around power-through-silicon via (TSV), a 6-phase read-data-strobe (RDQS) scheme, a byte-mapping swap scheme, and a voltage-drift compensator for write data strobe (WDQS), are implemented to achieve extended bandwidth and capacity with enhanced reliability. The overall architecture and specifications, such as bump map footprint, the number of channel and I/Os, and the operation voltage, are identical to the latest HBM3 1, 2; therefore, backward compatibility is provided, avoiding system modification.
There is enormous demand for high-bandwidth DRAM: in application such as HPC, graphics, high-end server and artificial intelligence. HBM DRAM was developed 1 using the advances in package technology: ...TSV, microbump and silicon-interposer. Owing to these advances, HBM has a much higher bandwidth, at a lower pin speed rate, than conventional DRAM. However, the 3D-stack structure causes TSV interface and PDN problems: TSV connection failure and 3D-accumulation of IR drop, which increases the total cost of HBM. Moreover, as memory bandwidth increases DRAM architectural challenges arise, power consumption and associated thermal problems increase as well.
Because of the expansion of high performance computing (HPC) and server market, demand for HBM DRAM is increasing. With this market flow, diverse customers require various HBM product families. One ...customer requirement is full bandwidth with less density. Therefore, this work presents a HBM DRAM, which supports 4, 8, and even 2-hi stacks with full-bandwidth performance. The HBM DRAM adopts a peripheral base die architecture, which has smaller chip size and good testability resulting in more manufacturability. This architecture can compensate for process variation, since this problem among core dies within the same known good stacked die (KGSD) is the key issue of TSV-based stacked DRAM 1. Layout aligning between PHY and TSVs improves the speed performance of the whole system due to reduced data skew. The peripheral base die contains address/command decoders (COMDEC), a core pipe-out (POUT) signal generator, and internal power, references and bias generators. A small-swing technique on a heavy load interface can reduce dynamic power and also has tolerance to process variations.
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