The development of devices that can modulate their conductance under the application of electrical stimuli constitutes a fundamental step towards the realization of synaptic connectivity in neural ...networks. Optimization of synaptic functionality requires the understanding of the analogue conductance update under different programming conditions. Moreover, properties of physical devices such as bounded conductance values and state-dependent modulation should be considered as they affect storage capacity and performance of the network. This work provides a study of the conductance dynamics produced by identical pulses as a function of the programming parameters in an HfO
memristive device. The application of a phenomenological model that considers a soft approach to the conductance boundaries allows the identification of different operation regimes and to quantify conductance modulation in the analogue region. Device non-linear switching kinetics is recognized as the physical origin of the transition between different dynamics and motivates the crucial trade-off between degree of analog modulation and memory window. Different kinetics for the processes of conductance increase and decrease account for device programming asymmetry. The identification of programming trade-off together with an evaluation of device variations provide a guideline for the optimization of the analogue programming in view of hardware implementation of neural networks.
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Emerging brain-inspired architectures call for devices that can emulate the functionality of biological synapses in order to implement new efficient computational schemes able to solve ill-posed ...problems. Various devices and solutions are still under investigation and, in this respect, a challenge is opened to the researchers in the field. Indeed, the optimal candidate is a device able to reproduce the complete functionality of a synapse, i.e., the typical synaptic process underlying learning in biological systems (activity-dependent synaptic plasticity). This implies a device able to change its resistance (synaptic strength, or weight) upon proper electrical stimuli (synaptic activity) and showing several stable resistive states throughout its dynamic range (analog behavior). Moreover, it should be able to perform spike timing dependent plasticity (STDP), an associative homosynaptic plasticity learning rule based on the delay time between the two firing neurons the synapse is connected to. This rule is a fundamental learning protocol in state-of-art networks, because it allows unsupervised learning. Notwithstanding this fact, STDP-based unsupervised learning has been proposed several times mainly for binary synapses rather than multilevel synapses composed of many binary memristors. This paper proposes an HfO
-based analog memristor as a synaptic element which performs STDP within a small spiking neuromorphic network operating unsupervised learning for character recognition. The trained network is able to recognize five characters even in case incomplete or noisy images are displayed and it is robust to a device-to-device variability of up to ±30%.
Random telegraph noise is a widely investigated phenomenon affecting the reliability of the reading operation of the class of memristive devices whose operation relies on formation and dissolution of ...conductive filaments. The trap and the release of electrons into and from defects surrounding the filament produce current fluctuations at low read voltages. In this work, telegraphic resistance variations are intentionally stimulated through pulse trains in HfO
-based memristive devices. The stimulated noise results from the re-arrangement of ionic defects constituting the filament responsible for the switching. Therefore, the stimulated noise has an ionic origin in contrast to the electronic nature of conventional telegraph noise. The stimulated noise is interpreted as raising from a dynamic equilibrium establishing from the tendencies of ionic drift and diffusion acting on the edges of conductive filament. We present a model that accounts for the observed increase of noise amplitude with the average device resistance. This work provides the demonstration and the physical foundation for the intentional stimulation of ionic telegraph noise which, on one hand, affects the programming operations performed with trains of identical pulses, as for neuromorphic computing, and on the other hand, it can open opportunities for applications relying on stochastic processes in nanoscaled devices.
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Investigations in the field of spiking neural networks (SNNs) encompass diverse, yet overlapping, scientific disciplines. Examples range from purely neuroscientific investigations, researches on ...computational aspects of neuroscience, or applicative-oriented studies aiming to improve SNNs performance or to develop artificial hardware counterparts. However, the simulation of SNNs is a complex task that can not be adequately addressed with a single platform applicable to all scenarios. The optimization of a simulation environment to meet specific metrics often entails compromises in other aspects. This computational challenge has led to an apparent dichotomy of approaches, with model-driven algorithms dedicated to the detailed simulation of biological networks, and data-driven algorithms designed for efficient processing of large input datasets. Nevertheless, material scientists, device physicists, and neuromorphic engineers who develop new technologies for spiking neuromorphic hardware solutions would find benefit in a simulation environment that borrows aspects from both approaches, thus facilitating modeling, analysis, and training of prospective SNN systems. This manuscript explores the numerical challenges deriving from the simulation of spiking neural networks, and introduces SHIP, Spiking (neural network) Hardware In PyTorch, a numerical tool that supports the investigation and/or validation of materials, devices, small circuit blocks within SNN architectures. SHIP facilitates the algorithmic definition of the models for the components of a network, the monitoring of states and output of the modeled systems, and the training of the synaptic weights of the network, by way of user-defined unsupervised learning rules or supervised training techniques derived from conventional machine learning. SHIP offers a valuable tool for researchers and developers in the field of hardware-based spiking neural networks, enabling efficient simulation and validation of novel technologies.
Bipolar resistive switching memories based on metal oxides offer a great potential in terms of simple process integration, memory performance, and scalability. In view of ultrahigh density memory ...applications, a reduced device size is not the only requirement, as the distance between different devices is a key parameter. By exploiting a bottom-up fabrication approach based on block copolymer self-assembling, we obtained the parallel production of bilayer Pt/Ti top electrodes arranged in periodic arrays over the HfO2/TiN surface, building memory devices with a diameter of 28 nm and a density of 5 × 1010 devices/cm2. For an electrical characterization, the sharp conducting tip of an atomic force microscope was adopted for a selective addressing of the nanodevices. The presence of devices showing high conductance in the initial state was directly connected with scattered leakage current paths in the bare oxide film, while with bipolar voltage operations we obtained reversible set/reset transitions irrespective of the conductance variability in the initial state. Finally, we disclosed a scalability limit for ultrahigh density memory arrays based on continuous HfO2 thin films, in which a cross-talk between distinct nanodevices can occur during both set and reset transitions.
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Spiking neural networks (SNNs) are a computational tool in which the information is coded into spikes, as in some parts of the brain, differently from conventional neural networks (NNs) that compute ...over real-numbers. Therefore, SNNs can implement intelligent information extraction in real-time at the edge of data acquisition and correspond to a complementary solution to conventional NNs working for cloud-computing. Both NN classes face hardware constraints due to limited computing parallelism and separation of logic and memory. Emerging memory devices, like resistive switching memories, phase change memories, or memristive devices in general are strong candidates to remove these hurdles for NN applications. The well-established training procedures of conventional NNs helped in defining the desiderata for memristive device dynamics implementing synaptic units. The generally agreed requirements are a linear evolution of memristive conductance upon stimulation with train of identical pulses and a symmetric conductance change for conductance increase and decrease. Conversely, little work has been done to understand the main properties of memristive devices supporting efficient SNN operation. The reason lies in the lack of a background theory for their training. As a consequence, requirements for NNs have been taken as a reference to develop memristive devices for SNNs. In the present work, we show that, for efficient CMOS/memristive SNNs, the requirements for synaptic memristive dynamics are very different from the needs of a conventional NN. System-level simulations of a SNN trained to classify hand-written digit images through a spike timing dependent plasticity protocol are performed considering various linear and non-linear plausible synaptic memristive dynamics. We consider memristive dynamics bounded by artificial hard conductance values and limited by the natural dynamics evolution toward asymptotic values (soft-boundaries). We quantitatively analyze the impact of resolution and non-linearity properties of the synapses on the network training and classification performance. Finally, we demonstrate that the non-linear synapses with hard boundary values enable higher classification performance and realize the best trade-off between classification accuracy and required training time. With reference to the obtained results, we discuss how memristive devices with non-linear dynamics constitute a technologically convenient solution for the development of on-line SNN training.
The charge trapping properties of HfO 2 thin films for application in charge trap memories are investigated as a function of high-temperature postdeposition annealing (PDA) and oxide thickness in the ...TaN/Al 2 O 3 /HfO 2 /SiO 2 /Si structure. The trap density ($N_{\text{T}}$) in HfO 2 , extracted by simulating the programming transient, is in the $10^{19}$--$10^{20}$ cm -3 range, and it is related to film thickness and PDA temperature. Diffusion phenomena in the stack play a significant role in modifying $N_{\text{T}}$ in HfO 2 and the insulating properties of the Al 2 O 3 layer. The memory performances for 1030 °C PDA are promising with respect to standard stacks featuring Si 3 N 4 .
Abstract
Women have made significant contributions to applied physics research and development, and their participation is vital to continued progress. Recognizing these contributions is important ...for encouraging increased involvement and creating an equitable environment in which women can thrive. This Roadmap on Women in Applied Physics, written by women scientists and engineers, is intended to celebrate women’s accomplishments, highlight established and early career researchers enlarging the boundaries in their respective fields, and promote increased visibility for the impact women have on applied physics research. Perspectives cover the topics of plasma materials processing and propulsion, super-resolution microscopy, bioelectronics, spintronics, superconducting quantum interference device technology, quantum materials, 2D materials, catalysis and surface science, fuel cells, batteries, photovoltaics, neuromorphic computing and devices, nanophotonics and nanophononics, and nanomagnetism. Our intent is to inspire more women to enter these fields and encourage an atmosphere of inclusion within the scientific community.
A metal/oxide/high-κ dielectric/oxide/silicon (MOHOS) planar charge trapping memory capacitor including SiO2 as tunnel oxide, Al–HfO2 as charge trapping layer, SiO2 as blocking oxide and TaN metal ...gate was fabricated and characterized as test vehicle in the view of integration into 3D cells. The thin charge trapping layer and blocking oxide were grown by atomic layer deposition, the technique of choice for the implementation of these stacks into 3D structures. The oxide stack shows a good thermal stability for annealing temperature of 900°C in N2, as required for standard complementary metal–oxide–semiconductor processes. MOHOS capacitors can be efficiently programmed and erased under the applied voltages of ±20V to ±12V. When compared to a benchmark structure including thin Si3N4 as charge trapping layer, the MOHOS cell shows comparable program characteristics, with the further advantage of the equivalent oxide thickness scalability due to the high dielectric constant (κ) value of 32, and an excellent retention even for strong testing conditions. Our results proved that high-κ based oxide structures grown by atomic layer deposition can be of interest for the integration into three dimensionally stacked charge trapping devices.
► Charge trapping device with Al–HfO2 storage layer is fabricated and characterized. ► Al–HfO2 and SiO2 blocking oxides are deposited by atomic layer deposition. ► The oxide stack shows a good thermal stability after annealing at 900°C. ► The device can be efficiently programmed/erased and retention is excellent. ► The oxide stack could be used for 3D-stacked Flash non-volatile memories.
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In the effort to ultimately shrink the size of logic devices towards a post-Si era, the integration of Ge as alternative channel material for high-speed p-MOSFET devices and the concomitant coupling ...with high permittivity dielectrics (high-
k) as gate oxides is currently a key-challenge in microelectronics. However, the Ge option still suffers from a number of unresolved drawbacks and open issues mainly related to the thermodynamic and electrical compatibility of Ge substrates with high-
k gate stack. Strictly speaking, two main concerns can be emphasized. On one side is the dilemma on which chemical/physical passivation is more suitable to minimize the unavoidable presence of electrically active defects at the oxide/semiconductor interface. On the other side, overcoming the SiO
2 gate stack opens the route to a number of potentially outperforming high-
k oxides. Two deposition approaches were here separately adopted to investigate the high-
k oxide growth on Ge substrates, the molecular beam deposition (MBD) of Gd
2O
3 and the atomic layer deposition (ALD) of HfO
2. In the MBD framework epitaxial and amorphous Gd
2O
3 films were grown onto GeO
2-passivated Ge substrates. In this case, Ge passivation was achieved by exploiting the Ge
4+ bonding state in GeO
2 ultra-thin interface layers intentionally deposited in between Ge and the high-
k oxide by means of atomic oxygen exposure to Ge. The composition of the interface layer has been characterized as a function of the oxidation temperature and evidence of Ge dangling bonds at the GeO
2/Ge interface has been reported. Finally, the electrical response of MOS capacitors incorporating Gd
2O
3 and GeO
2-passivated Ge substrates has been checked by capacitance–voltage measurements. On the other hand, the structural and electrical properties of HfO
2 films grown by ALD on Ge by using different oxygen precursors, i.e. H
2O, Hf(O
t
Bu)
2(mmp)
2, and O
3, were compared. Exploiting O
3 as oxidizing precursor in the ALD of HfO
2 is shown to play a beneficial role in efficiently improving the electrical quality of the high-
k/Ge interface through the pronounced formation of a GeO
2-like interface layer. In both cases, carefully engineering the chemical nature of the interface by the deliberate deposition of interface passivation layers or by the proper choice of ALD precursors turns out to be a key-step to couple high-
k materials with Ge.
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