Ever since the introduction of high bandwidth memory (HBM DRAM) and its succeeding line-ups, HBM DRAM has been heralded as a prominent solution to tackle the memory wall problem. However, despite ...continual memory advancements the advent of high-end systems, including supercomputers, hyper-scale data centers and machine learning accelerators, are expediting requirements for higher-performance memory solutions. To accommodate the increasing system-level demands, we introduce HBM3 DRAM, which employs multiple new features and design schemes. Techniques such as an on-die ECC engine, internal NN-DFE I/O signaling, TSV auto-calibration, and layout optimization based on machine-learning algorithms are implemented to efficiently control timing skew margins and SI degradation trade-offs. Furthermore, reduced voltage swings allow for improved memory bandwidth, density, power efficiency and reliability.
A 1 Gb density, 5.2 Gbps/s/pin data rate GDDR5 SDRAM was developed using 66 nm DRAM process. It uses traditional Core architecture, 8-bit pre-fetch with 16-banks, but the clocking and interface ...topology are fully changed for operating more than 4 Gbps without using differential signaling. Major barrier to achieving high data bandwidth is the clock jitter. To overcome this limitation, this project utilizes a CML clocking scheme.
