Transportation infrastructure is a critical component to a nation’s economy, security, and wellbeing. In order to keep up with the rising population, there is a great need for more efficient and ...cost-effective technologies and techniques to not only repair the infrastructure, but also to advance and expand the transportation infrastructure to sustain the growing population. Building Information Modeling (BIM) has been widely adopted in the building industry, and its established methods and technologies show enormous potential in benefiting the transportation industry. The purpose of this paper is to present a literature review and critical analysis of BIM for transportation infrastructure. A total of 189 publications in the area of BIM for transportation infrastructure were reviewed, including journal articles, conference proceedings, and published reports. Additionally, schemas and file formats from 9 main categories and 34 areas related to transportation infrastructure were reviewed. An application was developed to collect, store, and analyze the publications. Various algorithms were developed and implemented to help in the automation and analysis of the review. The goal of this paper is to provide a comprehensive, up-to-date literature review and critical analysis of research areas regarding BIM for transportation infrastructure to further facilitate research and applications in this domain. Based on the results of the analysis, current topics and trends, applications and uses, emerging technologies, benefits, challenges and limitations, research gaps, and future needs are discussed. Significantly, the contribution of this paper is providing the foundation of current research, gaps, and emerging technologies needed to facilitate further research and applications for both academia and industry stakeholders to develop more efficient and cost-effective techniques necessary to repair, advance, and expand the transportation infrastructure. Furthermore, the results show that the use of BIM for transportation infrastructure has been increasing, although the research has mainly been focusing on roads, highways, and bridges. The results also reveal a major need for a standard neutral exchange format and schema to promote interoperability. Most importantly, the continuing collaboration between academia and industry is required to mitigate most challenges and to realize the full potential of BIM for transportation infrastructure.
•A literature review of BIM for transportation infrastructure is presented.•189 publications are critically reviewed (Journals, Conferences Proceedings, and Reports).•Interoperability is a major challenge and there is a need for a neutral exchange.•Research gaps and emerging technologies are presented.•BIM has great potential for improving infrastructure.
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GEOZS, IJS, IMTLJ, KILJ, KISLJ, NLZOH, NUK, OILJ, PNG, SAZU, SBCE, SBJE, UL, UM, UPCLJ, UPUK, ZRSKP
Researchers worldwide are taking advantage of novel, commercially available, technologies, such as ion mobility mass spectrometry (IM‐MS), for metabolomics and lipidomics applications in a variety of ...fields including life, biomedical, and food sciences. IM‐MS provides three main technical advantages over traditional LC‐MS workflows. Firstly, in addition to mass, IM‐MS allows collision cross‐section values to be measured for metabolites and lipids, a physicochemical identifier related to the chemical shape of an analyte that increases the confidence of identification. Second, IM‐MS increases peak capacity and the signal‐to‐noise, improving fingerprinting as well as quantification, and better defining the spatial localization of metabolites and lipids in biological and food samples. Third, IM‐MS can be coupled with various fragmentation modes, adding new tools to improve structural characterization and molecular annotation. Here, we review the state‐of‐the‐art in IM‐MS technologies and approaches utilized to support metabolomics and lipidomics applications and we assess the challenges and opportunities in this growing field.
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BFBNIB, FZAB, GIS, IJS, KILJ, NLZOH, NUK, OILJ, SBCE, SBMB, UL, UM, UPUK
Compute-in-memory (CIM) is a promising technique that reduces data movement in neural network (NN) acceleration. To achieve higher efficiency, some recent CIM accelerators exploit NN sparsity based ...on CIM's small-grained operation unit (OU) feature. However, new problems arise in a practical multi-macro accelerator: The mismatch between workload parallelism and CIM macro organization causes spatial under-utilization; The multiple macros' different computation time leads to temporal under-utilization. To solve the under-utilization problems, we propose a Sparsity-balanced Practical CIM accelerator (SPCIM), including optimized dataflow and hardware architecture design. For the CIM dataflow design, we first propose a reconfigurable cluster topology for CIM macro organization. Then we regularize weight sparsity in the OU-height pattern and reorder the weight matrix based on the sparsity ratio. The cluster topology can be reshaped to match workload parallelism for higher spatial utilization. Each CIM cluster's workload is dynamically rebalanced for higher temporal utilization. Our hardware architecture supports the proposed dataflow with a spatial input dispatcher and a temporal workload allocator. Experimental results show that, compared with the baseline sparse CIM accelerator that suffers from spatial and temporal under-utilization, SPCIM achieves <inline-formula> <tex-math notation="LaTeX">2.94\times </tex-math></inline-formula> speedup and <inline-formula> <tex-math notation="LaTeX">2.86\times </tex-math></inline-formula> energy saving. The proposed sparsity-balanced dataflow and architecture are generic and scalable, which can be applied to other CIM accelerators. We strengthen two state-of-the-art CIM accelerators with the SPCIM techniques, improving their energy efficiency by <inline-formula> <tex-math notation="LaTeX">1.92\times </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">5.59\times </tex-math></inline-formula>, respectively.
Owing to the mature process and low access energy, static random-access memory (SRAM) has become a promising candidate for compute-in-memory (CiM) acceleration of multiply-accumulate (MAC) ...operations. However, SRAM-based CiM cells have rather low density and thus very limited total on-chip memory capacity. This fact, unfortunately, results in undesired weight data reload operations from the off-chip dynamic random-access memory (DRAM) in data-intensive scenarios and may even tarnish the energy efficiency of CiM at the task level. Therefore, exploration toward higher density CiM in CMOS is critical to ensure truly high energy efficiency in practice. Aligned with the goal of ultrahigh density, this article presents the first one-transistor (1T) multi-level-cell (MLC) read-only memory (ROM) CiM macro for multi-bit MAC. The highlights of the proposed ROM CiM techniques include: 1) multi-source-driven (MSD) 1T-MLC ROM; 2) charge-domain capacitor sharing (CDCS) for ultrahigh CiM memory density; and 3) ROM-based transfer-learning architectures to provide flexible support of different tasks with minor accuracy degradation. These techniques are demonstrated with a fabricated 2-Mb 1T-MLC ROM CiM macro for 8 b <inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> 8 b MAC computing. This macro features a record-high cell density of 0.096-<inline-formula> <tex-math notation="LaTeX">\mu \text{m}^{2} </tex-math></inline-formula>/bit and a macro weight density of 3984 kb/mm2 in a 65-nm pure CMOS technology. It also achieves 3.8<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula>-55.3<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> lower energy consumption per image inference than the state-of-the-art CiM macros when considering the possible DRAM access.
Under the von Neumann computing architecture, the edge devices used for artificial intelligence (AI) and the Internet of Things (IoTs) are limited in terms of latency and energy efficiency due to the ...movement of data between the memory and the processor. Nonvolatile memory-based computation-in-memory (nvCIM) is a promising candidate to overcome this issue, referred to as the memory wall. This article outlines the background and major challenges in the development of nvCIM macros as well as some of the recent progress in nvCIM for logic computation, pattern-matching computation, and multiply-and-accumulate (MAC) computation. We also summarize recent trends in nvCIM development at the end of each section.
Performing data-intensive tasks in the von Neumann architecture is challenging to achieve both high performance and energy efficiency due to the memory wall bottleneck. Compute-in-memory (CiM) is a ...promising mitigation approach by enabling parallel and in-situ multiply-accumulate (MAC) operations within the memory array. Thanks to the good matching of capacitors, SRAM-based charge-domain CiM (Q-CiM) has shown its potential for higher row-wise parallelism. However, the peripheral circuits of Q-CiM, such as the input drivers and analog-digital converters (ADCs), limit further improvement of throughput and area efficiency. This paper proposes a single-ADC multi-bit accumulation CiM macro architecture SAMBA, which can perform multi-bit MAC operation with ReLU of two vectors in one CiM cycle by only a single A/D conversion to mitigate the ADC overhead. In addition, post-correction methods are proposed to compensate the non-linearity of sensitive circuit modules in SAMBA to recover the accuracy drop due to the capacitor mismatch. A proof-of-concept macro is fabricated in a 65nm process and achieves 51.2GOPS throughput and 10.3TOPS/W energy efficiency, while showing 88.6% accuracy on CIFAR-10 and 64.8% accuracy on the CIFAR-100 with VGG-8 model.
This brief uses the capacitive charge coupling method to present a multi-bit SRAM-based compute-in-memory (CIM) architecture in the analog domain. The proposed architecture consists of a ...<inline-formula> <tex-math notation="LaTeX">64\times 64\,\,9 </tex-math></inline-formula>T1C SRAM array performing 1024 MAC operations between input activation (4-bit) and weight (4-bit) in a cycle, and an optimized 4-bit Flash ADC is used for converting the analog MAC into digital output. This brief achieves a throughput of 455 GOPS and an energy efficiency of 1012 TOPS/W at 222 MHz, maintaining a very high signal margin of 54 mV. The achieved inference accuracy is 98% for MNIST and 86% for the CIFAR-10 data set. This proposed work is implemented on a 28 nm CMOS Technology node at 0.9 V supply.
