Time-based analog-to-digital converters (ADCs) have recently gained attention because of their ability to reach high sample rates with good energy efficiency. The performance of most implementations ...is limited by the Voltage-to-Time Converter (VTC), hence necessitating thorough analysis on its performance. This paper derives expressions for the noise and linearity of a constant-slope VTC. The derived expressions provide an explicit link between the circuit parameters and VTC performance as well as offer insight on the available trade-offs. Based on the expressions, a general design methodology for constant-slope VTCs is proposed. The simulated verification with 28-nm CMOS shows good agreement with the presented analysis and with previously measured results, thereby corroborating the proposed design methodology. The presented design methodology allows the developed understanding between the VTC circuit parameters and performance metrics to be utilized in e.g. design exploration and algorithmic circuit optimization to find an optimal set of parameters for a given target specification.
In this paper, a fully integrated low-dropout regulator (LDO) using voltage-to-time conversion (VTC) technique is presented for under-1 V supply voltage application. A synchronous VTC technique is ...proposed using constant-current (CC) charging and discharging to achieve high loop gain. A high-gain charge pump (CP) is proposed to improve power-supply-rejection (PSR). Furthermore, an asynchronous step detection recovery technique is proposed to achieve fast transient response. A frequency-adaptive oscillator is proposed to remove the noise of the clock signal. The proposed LDO is designed in 28-nm process to achieve a droop voltage of 104 mV at load current transient of 90 mA. The proposed LDO achieves PSR of -77 dB at I LOAD =100 mA and PSR of -65 dB at I LOAD =10 mA for 1-kHz supply ripple frequency. The quiescent current is 32 µA and the peak current efficiency is 99.98%.
Résumé
Si les plateformes ont donné du travail à beaucoup d’Africains, les emplois créés sont de mauvaise qualité, comme la pandémie l'a bien montré. Dans ce contexte, les auteurs examinent la ...situation particulière des chauffeurs VTC en Afrique en s'appuyant sur des entretiens approfondis, réalisés au Kenya, et sur les méthodes de l'ethnographie virtuelle. Ils montrent que ces travailleurs ont recours à un «régime de débrouille», associant résilience, réajustement et résistance. Pour améliorer les conditions de travail et lutter contre la précarité dans le secteur, il faut à la fois que les pouvoirs publics instaurent des cadres réglementaires et que les travailleurs se mobilisent collectivement.
Full text
Available for:
FZAB, GIS, IJS, KILJ, NLZOH, NUK, OILJ, SBCE, SBMB, UL, UM, UPUK
In this paper, we have investigated the performance of a silicon-based low-doped drain (LDD) SOI-FinFET for the first time and compared it with conventional FinFET for implementation in logic ...circuits. It is well known that the use of the conventional LDD technology in the triple gate FinFETs reduces the electric field near the drain region and hot carrier effect at the cost of reduced current driving capability as is reported in LDD MOSFETs. We observe a reduction in the peak electric field by 15% near the drain region with a subsequent degradation in the electron velocity, as well. We have presented a semi-analytical approach to model the gate capacitance, drain current, channel potential, and subthreshold slope for the proposed FinFET structure. 3D simulation results for three different channel lengths using the TCAD Sentaurus tool are used to validate the computed results. DC analysis of the LDD-FinFET is performed and results are compared with the conventional FinFET device in terms of threshold voltage, transconductance, and
I
ON
/
I
OFF
ratio. The capacitance model is used to investigate the subthreshold swing and current driving capability of the proposed device. In addition to this, circuit-level analysis like voltage transfer characteristics and switching characteristic of proposed CMOS inverter using SOI LDD-FinFET is performed. The results presented in this paper can be utilized for the design of low-power digital applications to cater to the requirements of high switching speeds, high gain, and minimum power dissipation.
Full text
Available for:
DOBA, EMUNI, FIS, FZAB, GEOZS, GIS, IJS, IMTLJ, IZUM, KILJ, KISLJ, MFDPS, NLZOH, NUK, OBVAL, OILJ, PILJ, PNG, SAZU, SBCE, SBJE, SBMB, SBNM, SIK, UILJ, UKNU, UL, UM, UPUK, VKSCE, ZAGLJ
Depending on our goals, we pay attention to the global shape of an object or to the local shape of its parts, since it’s difficult to do both at once. This typically effortless process can be ...impaired in disease. However, it is not clear which cortical regions carry the information needed to constrain shape processing to a chosen global/local level. Here, novel stimuli were used to dissociate functional MRI responses to global and local shapes. This allowed identification of cortical regions containing information about level (independent from shape). Crucially, these regions overlapped part of the cortical network implicated in scene processing. As expected, shape information (independent of level) was mainly located in category-selective areas specialized for object- and face-processing. Regions with the same informational profile were strongly linked (as measured by functional connectivity), but were weak when the profiles diverged. Specifically, in the ventral-temporal-cortex (VTC) regions favoring level and shape were consistently separated by the mid-fusiform sulcus (MFS). These regions also had limited crosstalk despite their spatial proximity, thus defining two functional pathways within VTC. We hypothesize that object hierarchical level is processed by neural circuitry that also analyses spatial layout in scenes, contributing to the control of the spatial-scale used for shape recognition. Use of level information tolerant to shape changes could guide whole/part attentional selection but facilitate illusory shape/level conjunctions under impoverished vision.
•Modified Navon figures allow dissociation in time of fMRI responses for the global/local levels.•Shape-invariant hierarchical level information was found in scenes selective areas.•Level-invariant shape information was found in object- and faces- selective areas.•Level and shape regions were divided by the mid-fusiform sulcus (MFS) in VTC cortex, each connected into its own pathway.•Having separate level/shape pathways could facilitate selective-attention, but foster illusory conjunctions.
Full text
Available for:
GEOZS, IJS, IMTLJ, KILJ, KISLJ, NLZOH, NUK, OILJ, PNG, SAZU, SBCE, SBJE, UILJ, UL, UM, UPCLJ, UPUK, ZAGLJ, ZRSKP
In this brief, we present a high accuracy training method for inverter-based memristive neural networks ( IM -NNs). The method, which relies on accurate modeling of the circuit element ...characteristics, is called LATIM (Loading-Aware offline Training method for Inverter-based Memristive NNs). In LATIM, an approximation method is proposed to estimate the effective load of the memristive crossbar (as the synapses) while two NNs are utilized to predict the voltage transfer characteristic (VTC) of the inverters (as the activation functions). Efficacy of the proposed method is compared with the recent offline training methods for IM -NNs, called PHAX and RIM. Simulation results reveal that LATIM can predict the output voltage of the IM -NNs, on average, by <inline-formula> <tex-math notation="LaTeX">14\times </tex-math></inline-formula> (<inline-formula> <tex-math notation="LaTeX">6\times </tex-math></inline-formula>) and <inline-formula> <tex-math notation="LaTeX">29\times </tex-math></inline-formula> (<inline-formula> <tex-math notation="LaTeX">4\times </tex-math></inline-formula>) smaller error for the MNIST and Fashion MNIST datasets, respectively, compared to those of PHAX (RIM) method. In addition, IM -NNs trained by LATIM consume, on average, 62% and 53% lower energy compared to PHAX and RIM methods due to proper sizing of the inverters.
Polyphosphates (polyP) are energy-rich polymers of inorganic phosphates assembled into chains ranging from 3 residues to thousands of residues in length. They are thought to exist in all cells on ...earth and play roles in an eclectic mix of functions ranging from phosphate homeostasis to cell signaling, infection control, and blood clotting. In the budding yeast Saccharomyces cerevisiae, polyP chains are synthesized by the vacuole-bound vacuolar transporter chaperone (VTC) complex, which synthesizes polyP while simultaneously translocating it into the vacuole lumen, where it is stored at high concentrations. VTC's activity is promoted by an accessory subunit called Vtc5. In this work, we found that the conserved AP-3 complex is required for proper Vtc5 localization to the vacuole membrane. In human cells, previous work has demonstrated that mutation of AP-3 subunits gives rise to Hermansky-Pudlak syndrome, a rare disease with molecular phenotypes that include decreased polyP accumulation in platelet dense granules. In yeast AP-3 mutants, we found that Vtc5 is rerouted to the vacuole lumen by the
ndosomal
orting
omplex
equired for
ransport (ESCRT), where it is degraded by the vacuolar protease Pep4. Cells lacking functional AP-3 have decreased levels of polyP, demonstrating that membrane localization of Vtc5 is required for its VTC stimulatory activity
Our work provides insight into the molecular trafficking of a critical regulator of polyP metabolism in yeast. We speculate that AP-3 may also be responsible for the delivery of polyP regulatory proteins to platelet dense granules in higher eukaryotes.
Long polymers of inorganic phosphates called polyphosphates are ubiquitous across biological kingdoms. From bacteria to humans, they have diverse functions related to protein homeostasis, energy metabolism, and cell signaling. In this study, we provide new insights into the intracellular trafficking of the polyphosphate biosynthetic machinery in the budding yeast S. cerevisiae. The critical advances of the work are 2-fold. First, it provides an explanation for decreased polyphosphate levels observed in cells mutated for a conserved intracellular trafficking machine. Second, it defines critical pathways that are highly likely to serve as hubs for polyphosphate regulation in yeast and other species.
This paper presents a digital low-dropout regulator (D-LDO) with a proposed transient-response boost technique, which enables the reduction of transient response time, as well as ...overshoot/undershoot, when the load current is abruptly drawn. The proposed D-LDO detects the deviation of the output voltage by overshoot/undershoot, and increases its loop gain, for the time that the deviation is beyond a limit. Once the output voltage is settled again, the loop gain is returned. With the D-LDO fabricated on an 110-nm CMOS technology, we measured its settling time and peak of undershoot, which were reduced by 60% and 72%, respectively, compared with and without the transient-response boost mode. Using the digital logic gates, the chip occupies a small area of 0.04 mm 2 , and it achieves a maximum current efficiency of 99.98%, by consuming the quiescent current of 15 μA at 0.7-V input voltage.
A 6-bit 2.5-GS/s <inline-formula> <tex-math notation="LaTeX">8\times </tex-math></inline-formula> dynamic interpolating flash analog-to-digital converter (ADC) with an offset calibration technique ...for interpolated voltage-to-time converters (VTCs) is presented for high-speed applications. The dynamic-amplifier-structured VTC enables linear zero-crossing (ZX) interpolation in the time domain with an interpolation factor of 8, which reduces the number of front-end VTCs to one-sixth the original structure. The reduced number of VTCs lowers the power consumption, load capacitance to the track-and-holder (T/H), and overhead of VTC offset calibration. The sequential slope-matching offset calibration scheme is proposed not only for VTC offset but also for interpolated ZX accuracy. The prototype 6-bit 2.5-GS/s flash ADC was implemented in a 65-nm CMOS process and occupies a 0.12 mm 2 chip area, including offset calibration circuitry. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset calibration are 0.68 and 0.65 LSB, respectively. With a 1.23 GHz input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 33.84 and 45.07 dB, respectively, with power consumption of 7.5 mW under a supply voltage of 0.85 V. The prototype ADC achieves a figure of merit (FoM) of 74.7 fJ/conversion step at 2.5 GS/s.
PDF
