The CLAS12 Trigger System Raydo, B.; Boyarinov, S.; Celentano, A. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
04/2020, Volume:
960, Issue:
C
Journal Article
Peer reviewed
Open access
This article describes the CLAS12 Trigger System. The simulation, hardware, and software design, as well as all validation procedures, are discussed. The firmware development tools used are discussed ...as well, including our experience with VIVADO High Level Synthesis.
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GEOZS, IJS, IMTLJ, KILJ, KISLJ, NLZOH, NUK, OILJ, PNG, SAZU, SBCE, SBJE, UILJ, UL, UM, UPCLJ, UPUK, ZAGLJ, ZRSKP
Hydrogen will play a key part in the decarbonization of the global energy supply as the wealth of hydrogen continues to rise. However, applying hydrogen knowledge necessitates the installation of ...strong safety protocols, including the use of reliable hydrogen gas-detecting devices. Gas detection and monitoring at a large scale in industries need programmable electronic systems that can provide fast response and switching. The objective of the research work is to analyze the hydrogen gas detection system using a field programmable gate array (FPGA). The system is integrated with the gas sensor module, temperature control module, buzzer for alarm, liquid crystal display (LCD) and light-emitting diode (LED) for information display, and global system for mobile communication (GSM) for wireless message communication to the mobile. The temperatures module works on the sampling of the heater resistance using a voltage divider and inbuilt analog-to-digital converter (ADC), which depend on the output voltage of the digital-to-analog converter (DAC). The comparator module compares the gas concentration with the pre-decided threshold limit and acknowledges the buzzer accordingly. The system behavior for monitoring and gas concentration detection is simulated in Xilinx Vivado design suite 2020.1. The functionality of the chip is also verified in the Modelsim 10.0 waveform simulator. for the testbench tata sand samples used. LCD (16x2) displays the messages whether hydrogen gas is detected or not and the same message is delivered on mobile. The novelty of the work is that the system is applicable for faster switching in industrial applications and the designed system supported 550 MHz frequency in our simulation and synthesis.
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•Hydrogen gas detection and monitoring using FPGA for programmable electronic device switching.•Integration of gas sensor, temperature sensor, alarm, LCD, and GSM wireless communication.•Supports 550 MHz frequency for fast switching operations.•Chip assessment for hydrogen leakage identification, and validation on FPGA hardware.
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GEOZS, IJS, IMTLJ, KILJ, KISLJ, NLZOH, NUK, OILJ, PNG, SAZU, SBCE, SBJE, UILJ, UL, UM, UPCLJ, UPUK, ZAGLJ, ZRSKP
A Luenberger disturbance observer based control scheme for surface mounted permanent magnet synchronous motor (SPMSM) is proposed in this paper. First, an extended SPMSM model is given by considering ...the external disturbances and parameter mismatches. Second, a Luenberger observer is introduced to estimate the lumped disturbances in the speed and current loops, respectively. Third, based on the observed disturbances, a speed controller is designed, which is proved to be stable. Finally, an improved deadbeat-based predictive current control (DPCC) based on the estimated disturbances and the new SPMSM model is designed to control the current loop. The proposed method is implemented on a Xilinx Zynq SoC XC7Z020-CLG484-1 and field programmable gate array (FPGA) implementations of the improved DPCC and conventional DPCC are compared and analyzed in detail in terms of area utilization and time consumption. Although the execution time of both methods is very short, the improved DPCC takes less time than the conventional DPCC due to the parallel processing capabilities of FPGAs. The experimental results verify that the proposed method has good dynamic performance, load disturbance suppression performance, and parameter robustness.
The QUasi-Affine TRansformation Evolutionary (QUATRE) algorithm, a new intelligence optimization algorithm, has been widely used in many optimization fields. In this paper, a hardware-based QUATRE ...algorithm is designed and implemented on a field-programmable gate array (FPGA). To facilitate the implementation of the QUATRE algorithm on hardware, this paper simplifies the co-evolutionary matrix generation process. Compared with the original QUATRE algorithm, the simplified QUATRE algorithm may reduce latency and resource occupation. The Vivado High-Level Synthesis (HLS) design tool is used to complete the IP core design of the QUATRE algorithm. Through the benchmark function test under different population sizes, compared with the QUATRE algorithm implemented by software, both the running speed and optimization performance of the QUATRE algorithm implemented by hardware are significantly better than the former. Compared with the GA, DE, and PSO algorithms implemented by hardware, the QUATRE algorithm also shows strong competitiveness.
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GEOZS, IJS, IMTLJ, KILJ, KISLJ, NLZOH, NUK, OILJ, PNG, SAZU, SBCE, SBJE, UILJ, UL, UM, UPCLJ, UPUK, ZAGLJ, ZRSKP
Servo control systems are widespread used in modern industry as systems where the information processing and generation is primary instead of energy conversion. Their current evolution is remarkable ...both from technological and performances side. The aim of this paper is to demonstrate how can impact reconfigurable hardware technology (associated to last generation digital electronics) the design and implementation of modern servo systems. For this purpose a typical dc motor control application has been implemented upon a FPGA-based framework that embeds hardware reconfigurable technology. The physical implementation process has been completed then with last-generation software technologies application in order to enhance the achieved dynamic performances. The final result of the research and implementation efforts is a laboratory setup that exceeds with its versatility and flexibility. Exhibits modularized and compact hardware topology that may be easily reconfigured for a wide range of various servo control applications. Additionally, proves robustness and safety operation. The paper also unfolds the detailed design steps of the experimental test bench and presents precise measurement results. All these may be considered as a useful framework for future implementations of modern servo control systems.
This article proposes a hardware design of hand gesture recognition and its implementation on the Zynq platform (XC7Z020) of Xilinx. This proposed system is aimed to be embedded on the robotic ...prosthesis to improve the daily livings upper-limb amputees. Specifically, we design an architecture to identify hand movements using the Vivado HLS tool by exploiting the electromyography signal. The proposed architecture consists of creating two necessary intellectual properties (IPs) on hardware designed, tested, and validated against the software implementation. The first one performs feature extraction from the electromagnography (EMG) signal, and the second one implements the classification using the <inline-formula> <tex-math notation="LaTeX">{k} </tex-math></inline-formula>-nearest neighbor (k-NN) algorithm. Our framework process EMG signals acquired using an myo sensor with eight channels. The optimization of our design using pipeline directive achieves speed improvements of <inline-formula> <tex-math notation="LaTeX">5\times </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">2.15\times </tex-math></inline-formula> for the feature extraction and predict IPs, respectively, with moderate area resource consumption and the same performance as software implementation.
This article proposes an improved orthogonal matching pursuit (OMP) algorithm and its implementation with Xilinx Vivado high-level synthesis (HLS). We use the Gram-Schmidt orthogonalization to ...improve the update process of signal residuals so that the signal recovery only needs to perform the least-squares solution once, which greatly reduces the number of matrix operations in a hardware implementation. Simulation results show that our OMP algorithm has the same signal reconstruction accuracy as the original OMP algorithm. Our approach provides a fast and reconfigurable implementation for different signal sizes, different measurement matrix sizes, and different sparsity levels. The proposed design can recover a 128-length signal with measurement number <inline-formula> <tex-math notation="LaTeX">M=32 </tex-math></inline-formula> and sparsity <inline-formula> <tex-math notation="LaTeX">K=5 </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">K=8 </tex-math></inline-formula> in 13.2 and <inline-formula> <tex-math notation="LaTeX">21~\mu \text{s} </tex-math></inline-formula>, which is at least a 21.9% and 22.2% improvement compared with the existing HLS-based works; a 256-length signal with <inline-formula> <tex-math notation="LaTeX">M=64 </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">K=8 </tex-math></inline-formula> in <inline-formula> <tex-math notation="LaTeX">20.6~\mu \text{s} </tex-math></inline-formula>, which is a 24% improvement compared with the existing work; and a 1024-length signal with measurement number <inline-formula> <tex-math notation="LaTeX">M=256 </tex-math></inline-formula> and sparsity <inline-formula> <tex-math notation="LaTeX">K=12 </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">K=36 </tex-math></inline-formula> in 150.3 and <inline-formula> <tex-math notation="LaTeX">423~\mu \text{s} </tex-math></inline-formula>, respectively, which are close to the results of traditional hardware description language (HDL) implementations. Our results show that our improved OMP algorithm not only offers a superior reconstruction time compared with other recent HLS-based works but also can compete with existing works that are implemented using the traditional field-programmable gate array (FPGA) design route.
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