Abstract Major research interests on quantum key distribution (QKD) are primarily focused on increasing 1. Point-to-point transmission distance (1000 km). 2. Secure key rate (Mbps). 3. Security of ...quantum layer (device-independence). It is great to push the boundaries in these fronts but these isolated approaches are neither scalable nor cost-effective due to requirements of specialised hardware and different infrastructure. Current and future QKD network requires addressing different set of challenges apart from distance, key rate and quantum security. In this regard, we present ChaQra—a sub quantum network with core features as 1. Crypto agility (integration in the already deployed telecommunication fibres). 2. Software defined networking (SDN paradigm for routing different nodes). 3. reliability (addressing denial-of-service with hybrid quantum safe cryptography). 4. upgradability (modules upgradation based on scientific and technological advancements). 5. Beyond QKD (using QKD network for distributed computing, multi-party computation etc). Our results demonstrate a clear path to create and accelerate quantum secure Indian subcontinent under national quantum mission.
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IZUM, KILJ, NUK, PILJ, PNG, SAZU, UL, UM, UPUK
2.
From the archive
Nature (London),
06/2023, Volume:
618, Issue:
7963
Journal Article
Peer reviewed
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Available for:
GEOZS, IJS, IMTLJ, KISLJ, NLZOH, NUK, OILJ, PNG, SAZU, SBCE, SBMB, UL, UM, UPUK, ZAGLJ
In the paper, we present a new method to study the differential properties of addition modulo 2 n using the formulas of coefficients of sum of 2-adic integers.
To improve the efficiency of lattice-based cryptography in practical applications, the optimization technology of polynomial multiplication in lattice-based cryptography is proposed. The polynomial ...coefficients are stored in a ping-pong structure to improve the bandwidth. By eliminating pre-scale operations, 10.5% of modular multiplication operations and 16.7% of storage space are saved. The structure based on look-up table shift register and three-input adder is adopted to reduce the logical resource occupation. The pipeline structure with optional stages is designed to make the butterfly module in polynomial multiplication meet the timing requirements of different cryptographic hardware systems. The evaluation results show that the maximum frequency of low-area, balanced and high-performance implementations of the optimized butterfly unit can reach 150, 250 and 350 MHz, respectively. Compared with the existing implementation technologies, the optimized hardware implementation can achieve higher operating fr