E-resources
Peer reviewed
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Jian-Hsing Lee; Iyer, Natarajan Mahadeva; Prabhu, Manjunatha
IEEE electron device letters 38, Issue: 5Journal Article
A novel high electrostatic discharge (ESD), robust fully salicided 5-V integrated CMOS power MOSFET design is developed and demonstrated without the use of conventional salicide blocking ballast resistor. This scheme builds the ballast resistors on the top of the source and drain, without any increase in silicon footprint unlike prior methods, while maintaining standard transistor parametric performance.
