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Garzetti, F.; Corna, N.; Lusardi, N.; Costa, A.; Ronconi, E.; Salgaro, S.; Geraci, A.; Brajnik, G.; Carrato, S.; Cautero, G.; Cautero, M.; Sergo, R.; Stebel, L.
2021 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2021-Oct.-16Conference Proceeding
The utilization of time-based approaches in modern physics experiments, has seen continuous growth thanks to the increasing performance of modern time-interval-meters (TIMs). In this context, Time-to-Digital Converters (TDCs), that are fully-digital TIMs, play a fundamental role. The digital approach makes the integration into measurement setups easier, while giving the possibility to investigate time-events with picosecond resolution over extended dynamic-ranges. Cross Delay-Lines (CDL) detectors are remarkably valuable, due to the fact that the position of the event can be detected by measuring the time of arrival, obtaining both information at once. With the purpose of achieving both fast parallel computing and time precision, the conventional acquisition systems usually count on 4-channel Application Specific Integrated Circuit (ASIC) Time-to-Digital Converters (TDCs) preceding a Field Programmable Logic Array (FPGA), reaching state-of-the-art performance in time resolved experiments. In this kind of architecture, the lack of reconfigurability, given by the ASIC, is a tightly limiting factor when customization of the setup is required, even more so at present day, where state-of-the-art TDCs with performance similar to ASICs can be fully implemented on FPGAs; for this reason, we propose a fully-FPGA based approach to this problem, in order to obtain a complete real-time system that can be completely reconfigured in function of the experimental setup. With the aim of improving the accuracy of the experiments, the time correlation between the CDL and the arrival time of other events occurring in conjunction is essential. For this reason, auxiliary TDC channels are needed. In this contribution, we present a compact, powerful and fully-configurable FPGA-based solution, where an 8-channel TDC with a precision of 12 ps r.m.s. and the related real-time image reconstruction algorithm are performed on two different FPGA devices. In this sense, a spatial resolution on the CDL of 50/60 µm FWHM is achieved.
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