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Mathieu, Gaudron; Guy, Bois; Jerome, Hugues; Monteiro, Fellipe
2015 International Symposium on Rapid System Prototyping (RSP), 10/2015Conference Proceeding, Journal Article
One of the key issues to ensure high-quality designs is the verification methodology. The typical verification methodology used for RTL design is based on the V diagram. In this article we work at higher levels of abstraction (named ESL) by focusing on the performance verification process. A subsystem and its interconnected components are modeled with AADL. AADL also contains constructs for modeling both software and hardware components. Through the ESL virtual platform SpaceStudio TM , we can rapidly estimate the performance on different architectures. This performance verification flow has been experimented on a Motion-JPEG video decoder application for video thumbnails that targets a Xilinx Zynq-7000 platform.
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