Enhanced CDM-robustness for the packaged IC with the extra bonding wire to the die-attach plate

E-resources

Enhanced CDM-robustness for the packaged IC with the extra bonding wire to the die-attach plate

Tzu-Cheng Kao; Jian-Hsing Lee; Chen-Hsin Lien; Chih-Hsien Wang; Kuang-Cheng Tai; Hung-Der Su

2015 IEEE International Reliability Physics Symposium, 2015-April

Conference Proceeding

From the experimental measurements, the dominant charge source for a packaged IC chip during a charged-device model (CDM) ESD event is the capacitor between the die-attach plate and the metal bus line, C SUB . By adding a bonding wire between the die-attach plate and the Vss pin, a parallel inductor to the C SUB can be created. The CDM-robustness for the packaged IC chip is significantly improved because of this parallel LC resonance circuit.

Keep searching

Author

Access to the JCR database is permitted only to users from Slovenia. Your current IP address is not on the list of IP addresses with access permission, and authentication with the relevant AAI accout is required.

Year	Impact factor		Edition		Category		Classification
Year	JCR	SNIP	JCR	SNIP	JCR	SNIP	JCR	SNIP

Links to authors' personal bibliographies	Links to information on researchers in the SICRIS system

Source: Personal bibliographies and: SICRIS

Upload image

Shelf entry

Adding material to shelf was successful.

Adding material to shelf failed.

It was not necessary to add the material to the shelf.

Permalink

E-mail

Impact factor

Select the library membership card:

DRS, in which the journal is indexed

Citations

Theme