A 32-channel 840Msps TDC based on Altera Cyclone III FPGA

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A 32-channel 840Msps TDC based on Altera Cyclone III FPGA

Grigoriev, D.N.; Kasyanenko, P.V.; Kravchenko, E.A.; Shamov, A.G.; Talyshev, A.A.

Journal of instrumentation, 08/2017, Volume: 12, Issue: 8

Journal Article

In this work we present a newly developed TDC (Time-to-Digital Converter) board in the VME-32 standard. The 32-channel TDC board is based on a single FPGA Altera Cyclone III chip. The main parameters of the TDC are as follows: a resolution of 1.19 ns, a dead time of 4.76 ns, and a maximal time interval of 19 504 ns.

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Author

Grigoriev, D.N. | Kasyanenko, P.V. | Kravchenko, E.A. | Shamov, A.G. | Talyshev, A.A.

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