This paper discusses energy efficient ADC design with low voltage operation. In SAR ADCs, the energy consumption stays constant in the S&H circuit and increases in the comparator with supply voltage, V DD . However, the energy consumed by the logic gates can be reduced using low V DD . Thus, the optimum V DD which minimizes the total energy consumption in SAR ADCs can be found. In flash ADCs, the ENOB is mainly determined by mismatch voltages of the comparators and the energy consumption can be reduced by using lower V DD ; however, it also reduces conversion frequency. Thus, we proposed FoM delay product (FD product) that offers the balance between the energy consumption and conversion speed. The optimum V DD that minimizes FD product can be found. A 0.5 V 5-bit 600 MSps flash ADC has been developed and demonstrated the usefulness of reducing V DD to decrease the energy consumption without serious degradation of the performance.