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Celotno besedilo
  • Low-power variation-tolerant design in nanometer silicon [Elektronski vir]
    Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, ... dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance
    Vrsta gradiva - e-knjiga
    Založništvo in izdelava - New York : Springer, ©2011
    Jezik - angleški
    ISBN - 978-1-4419-7418-1; 1-4419-7418-0
    COBISS.SI-ID - 1543366367

    Povezava(-e):

    SpringerLink e-books 2008-2012

    Celotno besedilo dostopno za uporabnike SpringerLink slovenskega konzorcija neprofitnih institucij

    Full text accessible to the users of SpringerLink Slovenian Consortium of Non-Profit Institutions


    DOI

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