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  • Digitalno FIR sito s 64 koeficienti in standardnim mikroprocesorskim vmesnikom realizirano v FPGA vezju
    Kramberger, Iztok ; Solar, Mitja
    In this article the realization of 64-tap digital FIR filter with standard microprocesor interface in a FPGA is represented. It was realized in a single Atmel's FPGA circuit AT40K20. Using standard ... microprocessor interface the FIR filter is easy to use with common DSP microprocessors. It can be used as a DSP coprocessor to increase the computing power of the DSP. Acceleration hardware has the capability to exchange the filter coefficients through write cycles. Input and output samples are written and read through a single data bus. The input samples and coefficients are in 16-bit wide 2's complement data format and the output samples are in 2's complement 32-bit wide data format. The arithmetic of the filter is based on direct implementation of convolutiom algorithm. For the measurement of frequency response and stop bandattenuation of the digital FIR filter the digital white noise signal has been used.
    Vir: Zbornik osme Elektrotehniške in računalniške konference ERK '99, 23. - 25. september 1999, Portorož, Slovenija (Zv. A, str. 63-66)
    Vrsta gradiva - prispevek na konferenci
    Leto - 1999
    Jezik - slovenski
    COBISS.SI-ID - 4806678

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