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  • Correlation coprocessor for multichannel CDMA receiver
    Vicman, Peter ; Balan, Filip Samo ; Brezočnik, Zmago
    The article presents a realization of correlator in FPGA (Field Programmable Gate Array) circuit for a multichannel CDMA (Code Division Multiple Access) receiver. It acts like a coprocessor to a DSP ... (Digital Signal Processor), which performs other necessary operations for reception. Some basic information about systems with code division multiple access and correlation are presented. The architecture of the correlator is described. In the reception phase the input signal is first digitized by rapid A/D converters. Next, the corelation sum for all channels in FPGA circuit is calculated. The value obtained through calculation is transfered to the processor on its demand. The processor comunicates with the coprocessor over registers. The formation of local pseudo-random sequences, the correlation with the input signal, and the communication with the processor were described in VHDL.
    Vir: Advances in signal processing and computer technologies (Str. 261-264)
    Vrsta gradiva - prispevek na konferenci
    Leto - 2001
    Jezik - angleški
    COBISS.SI-ID - 6385686

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