Ultrasonic Transducer in the wire bonding machine is a key component to determine its bonding speed, and is demanded to be downsized with keeping high rigidity performance for high-speed bonding ...process. In this paper, a modeling of the ultrasonic transducer vibration and a new ultrasonic transducer with slit structure near the fixation parts is discussed. The piezoelectric element designed by an analytical model has 45% lighter weight than the conventional one. The slit type ultrasonic transducer newly proposed and simulation by finite element method has 66% lighter weight and 2.44-times higher rigidity than the conventional one. As a result, the slit type ultrasonic transducer enable 200G acceleration motion at Z direction of wire bonder from 160G by previous one and it shorten 33% of rising ultrasonic vibration time. Finally, it makes 17% faster cycle time to make wire, it has a potential to improve productivity a lot.
A Si pn junction diode-based electron beam detector with high sensitivity at low acceleration voltage and high readout speed is reported, by using steep pn junction formation technology. A high ...sensitivity wide spectral response photodiode using high concentration surface layer with steep impurity concentration profile was applied to the detector in order to enhance sensitivity performance toward low acceleration voltage incident electron with short penetration depth in Si. A 51.8% quantum efficiency at 1kV acceleration voltage was obtained. Also, a reduction of detector’s capacitance was obtained by introducing low concentration Si substrate and multiple signal readout structure for improvement of signal readout speed.
本稿では急峻pn接合Siダイオード技術を用いた高感度・高速性能を有する低加速電圧電子線検出器について報告する．薄くて急峻な不純物濃度プロファイルを有する表面高濃度層を用いた紫外-可視-近赤外光高感度フォトダイオード技術を応用して Si中への侵入長が短い低加速電圧電子線に対する感度を向上させ，加速電圧1kVにおいて 51.8%の量子効率を得ると共に，低不純物濃度Si基板と素子感度領域の分割構造の導入により信号読出しの高速化に資する素子容量の低減を行った．
This paper presents an over 1Mfps CMOS image sensor with on-chip 480 memories per pixel using high density analog memory integration technology. The prototype chips with 96H×128V pixels were ...fabricated with various memory fabrication condition and ultra-high speed video capturing at 1Mfps with 480 /960 frames is successfully demonstrated.
高密度アナログメモリを導入し，480オンチップメモリ/画素を搭載した100万コマ/秒超の高速CMOSイメージセンサについて報告する．96H×128V画素のプロトタイプセンサを複数の高密度容量形成条件で試作し，100万コマ/秒，記録枚数480 /960コマのバースト撮像を実証した．
In this work, statistical analyses of random telegraph noise (RTN) at in-pixel source followers using array test circuit are reported with following two focuses. The first one is the impact of time ...constants and number of states toward readout noise in CMOS image sensors. The other one is the impact of transistor shapes. SF transistors with various shapes including rectangular, trapezoidal and octagonal structures were analyzed and reduction effect of RTN is summarized.
本稿ではアレイテスト回路を用いた画素ソースフォロワトランジスタのランダムテレグラフノイズ（RTN）に関する以下の 2項目に焦点を当てた統計的解析について報告する．一つ目は，時定数および状態遷移数が CMOSイメージセンサの読出しノイズに与える影響である．二つ目は，ソースフォロワトランジスタの形状が与える影響に関する解析であり，通常の長方形のゲート構造に加えて八角形や非対称型のソース・ドレイン構造を有する台形レイアウトのトランジスタを測定して明らかにした RTN低減効果をまとめる．
An almost 100% temporal aperture (dead-time free) global shutter (GS) stacked CMOS image sensor (CIS) with in-pixel lateral overflow integration capacitor (LOFIC), 12bit single slope ADC and DRAM is ...developed using pixel-wise connections. The prototype chip with 6.6μm-pitch VGA LOFIC pixel dead-time free GS mode and 1.65μm-pitch 4.9M sub-pixel high resolution rolling shutter (RS) mode was fabricated with a 45nm 1P4M CIS technology for PD substrate and a 65nm 1P5M CMOS technology forASIC substrate. The detail of design, fabricationand measurement results are described.
画素毎の接続を用いた画素内に横型オーバーフロー蓄積容量（ LOFIC）および 12ビットシングルスロープ型 AD変換器を有する露光時間途切れのないグローバルシャッタ積層型 CMOSイメージセンサについて報告する． 45nmノード 1P4M CMOSイメージセンサテクノロジをフォトダイオード基板に， 65nmノード 1P5M CMOSテクノロジを ASIC基板に適用し， 6.6μmピッチで VGAサイズの LOFICを有するグローバルシャッタモードと，1.65μmピッチで画素数 4.9Mの高精細ローリングシャッタモードを実装したプロトタイプチップの設計・試作および測定を行ったので，その内容について論じる．
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