The ALPIDE chip is a CMOS Monolithic Active Pixel Sensor being developed for the Upgrade of the ITS of the ALICE experiment at the CERN Large Hadron Collider. The ALPIDE chip is implemented with a ...180nm CMOS Imaging Process and fabricated on substrates with a high-resistivity epitaxial layer. It measures 15mm×30mm and contains a matrix of 512×1024pixels with in-pixel amplification, shaping, discrimination and multi-event buffering. The readout of the sensitive matrix is hit driven. There is no signaling activity over the matrix if there are no hits to read out and power consumption is proportional to the occupancy. The sensor meets the experimental requirements of detection efficiency above 99%, fake-hit probability below 10−5 and a spatial resolution of 5μm. The capability to read out Pb–Pb interactions at 100kHz is provided. The power density of the ALPIDE chip is projected to be less than 35mW/cm2 for the application in the Inner Barrel Layers and below 20mW/cm2 for the Outer Barrel Layers, where the occupancy is lower. This contribution describes the architecture and the main features of the final ALPIDE chip, planned for submission at the beginning of 2016. Early results from the experimental qualification of full scale prototype predecessors are also reported.
•The ALPIDE chip, an innovative CMOS pixel particle detector is described.•It achieves excellent detection performance figures and very low power consumption.•The characterization of prototypes confirms the achievement of the specifications.
Digital pixel test structures implemented in a 65 nm CMOS process Aglieri Rinella, Gianluca; Andronic, Anton; Antonelli, Matias ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
11/2023, Letnik:
1056
Journal Article
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The ALICE ITS3 (Inner Tracking System 3) upgrade project and the CERN EP R&D on monolithic pixel sensors are investigating the feasibility of the Tower Partners Semiconductor Co. 65nm process for use ...in the next generation of vertex detectors. The ITS3 aims to employ wafer-scale Monolithic Active Pixel Sensors thinned down to 20–40µm and bent to form truly cylindrical half barrels. Among the first critical steps towards the realisation of this detector is to validate the sensor technology through extensive characterisation both in the laboratory and with in-beam measurements. The Digital Pixel Test Structure (DPTS) is one of the prototypes produced in the first sensor submission in this technology and has undergone a systematic measurement campaign whose details are presented in this article.
The results confirm the goals of detection efficiency and non-ionising and ionising radiation hardness up to the expected levels for ALICE ITS3 and also demonstrate operation at ＋20°C and a detection efficiency of 99% for a DPTS irradiated with a dose of 10151MeV neq cm-2. Furthermore, spatial, timing and energy resolutions were measured at various settings and irradiation levels.
The ALICE experiment at the CERN LHC will feature several upgrades for Run 3, one of which is a new Inner Tracking System (ITS). The ITS upgrade is currently under development and commissioning, and ...will be installed during the ongoing long shutdown 2.
A number of factors will have an impact on the performance and readout efficiency of the ITS in run 3, and to that end, a simulation model of the readout logic in the ALPIDE pixel sensor chips for the ITS was developed, using the SystemC library for system level modeling in C++. This simulation model is three orders of magnitude faster than a normal HDL simulation of the chip and facilitates simulations of an increased number of events for a large portion of the detector.
In this paper, we present simulation results, where we have been able to quantify detector performance under different running conditions. The results are used for system configuration as well as for the ongoing development of the readout electronics.
We derive expressions for the time resolution of silicon detectors, using the Landau theory and a PAI model for describing the charge deposit of high energy particles. First we use the centroid time ...of the induced signal and derive analytic expressions for the three components contributing to the time resolution, namely charge deposit fluctuations, noise and fluctuations of the signal shape due to weighting field variations. Then we derive expressions for the time resolution using leading edge discrimination of the signal for various electronics shaping times. Time resolution of silicon detectors with internal gain is discussed as well.
In this work the initial performance studies of the first small monolithic pixel sensors dedicated to charged particle detection, called CE-65, fabricated in the 65nm TowerJazz Panasonic ...Semiconductor Company are presented. The tested prototypes comprise matrices of 64×32 square analogue-output pixels with a pitch of 15μm. Different pixel types explore several sensing node geometries and amplification schemes, which allows for various biasing voltage of the detection layer and hence depletion conditions and electric field shaping. Laboratory tests conducted with a 55Fe source demonstrated that the CE-65 sensors reach equivalent noise charge in the 15 to 25e− range and excellent charge collection efficiencies. Charge sharing is substantial for standard diodes, but can be largely suppressed by modifying their design. Depletion of the thin sensitive layer saturates at a reverse diode bias of about 5 V.
The TDCpix is a novel readout ASIC for hybrid pixel detectors with emphasis on timing. It is designed to meet the requirements of the Gigatracker, the kaon spectrometer of the NA62 experiment at the ...CERN Super Proton Synchrotron. The Gigatracker consists of three tracking and time-tagging hybrid pixel modules. A time resolution better than 200 ps is required. The silicon pixel sensors will be 60×27 mm 2 and 200 μm thick. A pixel size of 300×300 μm 2 will provide the required position and momentum resolution. Each sensor will be read out by 2×5 TDCpix ASICs, connected by flip-chip bonding. The main capabilities of the TDCpix chip will be to detect and time stamp more than 130 million charged particle hits per second (>0.8 MHz/mm 2 ) with a timing resolution below 200 ps (RMS). This contribution describes the completed and final design of the TDCpix ASIC. The chip has been designed in a 130 nm CMOS process. It combines a matrix of 45×40 pixel channels with amplifying and discriminating circuits and a complex peripheral region including an array of TDCs based on DLLs, four high speed (3.2 Gb/s) data serializers, a low-jitter PLL, bandgap references, DACs, readout and control circuits. Mandatory correction of the time-walk of the discriminator leading edge is based on the measurement of Time over Threshold. The laboratory characterization of a prototype chip demonstrated a resolution better than 75 ps RMS for injected charges larger than 2 fC and constant pulse shapes. The achievement of the target timing resolution with real particles has been demonstrated in beam tests using prototype chips and prototype hybrid modules.
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