In recent years, silicon photomultiplier (SiPM) technology has been getting attention from various applications due to its low cost, immunity to magnetic field, compactness and ruggedness. However, ...its applicability in experiments with harsh radiation environments is still limited due to lack of corresponding radiation damage studies. A 10-year lifetime operation in a typical Small Angle Neutron Scattering (SANS) experiment with an acceptable degradation in photon detection efficiency has already been reported. In this article, we discuss the feasibility study of SiPM technology in neutron time of flight experiments. For this purpose, two analog SiPMs, developed by SensL and Hamamatsu, have been irradiated with cold neutrons (5 Å ) up to a dose of 6ċ1012 n/cm2 at the KWS-1 instrument of the Heinz Maier-Leibnitz Zentrum (MLZ) in Germany. After irradiation, the timing resolutions of the SiPMs have been measured under pulsed laser beam with a few hundred photons (405 nm) per pulse, and a degradation of up to 6 ps has been observed. The degradation might be a result of noise increase, introduced by surface defects caused by neutron exposure damage. Additionally, variation of the excess voltage helped to reveal the difference in the timing resolutions between irradiated and non-irradiated SiPMs, which remained almost constant.
Abstract
We measured the surface tension of linear alkylbenzene (LAB)
HYBLENE 113 mixed with Diphenyloxazole (PPO) as well as of pure LAB
HYBLENE 113 as part of material studies for the ...liquid-scintillator
based surround background tagger (SBT) in the proposed SHiP
experiment. The measurement was performed using the iron wire method
and the surface tension for linear alkyl benzene HYBLENE 113 plus
PPO was found to be (30.0 ± 0.6) mN/m 22.0 ± 0.5°C and
for pure HYBLENE 113, (29.2 ± 0.6) mN/m at
21.0 ± 0.5°C.
The FE-I4 is a new pixel readout integrated circuit designed to meet the requirements of ATLAS experiment upgrades. The first samples of the FE-I4 engineering run (called FE-I4A) delivered promising ...results in terms of the requested performances. The FE-I4 team envisaged a number of modifications and fine-tuning before the actual exploitation, planned within the Insertable B-Layer (IBL) of ATLAS. As the IBL schedule was pushed significantly forward, a quick and efficient plan had to be devised for the FE-I4 redesign. This article will present the main objectives of the resubmission, together with the major changes that were a driving factor for this redesign. In addition, the top-level verification and test efforts of the FE-I4 will also be addressed.
A new ATLAS pixel front-end IC for upgraded LHC luminosity Barbero, M.; Arutinov, D.; Beccherle, R. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
06/2009, Letnik:
604, Številka:
1
Journal Article
Recenzirano
A new pixel Front-End (FE) IC is being developed in a 130
nm technology for use in the upgraded ATLAS pixel detector. The new pixel FE will be made of smaller pixels (50×250
μm vs. 50×400
μm for the ...present FE, FE-I3), a much improved active area over inactive area ratio, and a new analog pixel chain tuned for low power and new detector input capacitance. The higher luminosity for which this IC is tuned implies a complete redefinition of the digital architecture logic, which will not be based on End-of-Column data buffering but on local pixel logic and local pixel data storage. An overview of the new FE is given with particular emphasis on the new digital logic architecture and possible architecture variations.
The FE-I4 pixel readout integrated circuit Garcia-Sciveres, M.; Arutinov, D.; Barbero, M. ...
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment,
04/2011, Letnik:
636, Številka:
1
Journal Article, Conference Proceeding
Recenzirano
Odprti dostop
A new pixel readout integrated circuit denominated FE-I4 is being designed to meet the requirements of ATLAS experiment upgrades. It will be the largest readout IC produced to date for particle ...physics applications, filling the maximum allowed reticle area. This will significantly reduce the cost of future hybrid pixel detectors. In addition, FE-I4 will have smaller pixels and higher rate capability than the present generation of LHC pixel detectors. Design features are described along with simulation and test results, including low power and high rate readout architecture, mixed signal design strategy, and yield hardening.
To face new challenges brought by the upgrades of the Large Hadron Collider at CERN and of the ATLAS pixels detector, for which high spatial resolution, very good signal to noise ratio and high ...radiation hardness is needed, 3D integrated technologies are investigated. In the years to come, the Large Hadron Collider will be upgraded to Higher Luminosity (HL-LHC). The ATLAS pixel detector needs to handle this new challenging environment. As a consequence, 3D integrated technologies are pursued with the target of offering higher spatial resolution, very good signal to noise ratio and unprecedented radiation hardness. We present here the test results of the first 3D prototype chip developed in the GlobalFoundries 130 nm technology processed by the Tezzaron Company, submitted within the 3D-IC consortium for which a qualification program was developed. Reliability and influence on the behavior of the integrated devices due to the presence of the Bond Interface (BI) and of the Through Silicon Via (TSV) connections, both needed for the 3D integration process, have also been addressed by the tests.
The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve ...the tolerance to SEU. Tests have shown that DICE latches for which layout approaches are adopted are 30 times more tolerant to SEU than the standard DICE latches. To prepare for the new pixel readout chip planned for the future upgrades, a prototype chip containing 512 pixels has been designed in a 65 nm CMOS process and a new approach is adopted for SEU tolerant latches. Results in terms of SEU and TID tolerance are presented.
This paper describes an original Design-for-Test (DfT) architecture implemented in the ATLAS FE-I4 pixel readout System-on-Chip (Soc) to accommodate the higher quality demands of future generation ...LHC detectors. To ensure that the highest possible number of fault-free devices is used for the detector construction, the so-called production test to detect faulty devices after the manufacturing has to be executed. For that reason, we devised a straightforward and effective DfT circuitry inside the digital part of the FE-I4 that will enable high fault coverage of potential structural faults while maintaining the performance and area penalties of the entire design negligible.
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