Quality of Experience (QoE) is a critical aspect of multimedia applications, which directly impacts user satisfaction and adoption. QoE predictions are used to optimize various parameters such as ...video quality, bitrate, and network bandwidth to enhance the user experience. However, accurate QoE prediction is a challenging task, as it involves various factors such as network conditions, video content, and user preferences. Therefore, there is a need for enhancing QoE predictions with advanced techniques to improve user satisfaction and adoption. This paper proposes incorporating more complex neural network architectures and using more diverse datasets to improve the accuracy and generalization of Quality of Experience (QoE) predictions. The paper suggests experimenting with more advanced architectures such as convolutional neural networks and recurrent neural networks, which have been shown to be effective in various applications. Additionally, the paper highlights the limitation of using a single dataset and proposes using more diverse datasets that capture different types of video content and network conditions. Enhancing QoE predictions with complex neural networks and diverse datasets include improved accuracy, better generalization, more sophisticated models, enhanced user satisfaction and increased adoption. These enhancements are expected to lead to more accurate and reliable QoE predictions, which are crucial for improving user experience in multimedia applications.
Celotno besedilo
Dostopno za:
DOBA, IZUM, KILJ, NUK, PILJ, PNG, SAZU, UILJ, UKNU, UL, UM, UPUK
A series of new phosphorylated derivatives of didanosine were designed, synthesized and evaluated their anticancer effects on human breast cancer cells. Their binding affinities were evaluated ...against aromatase enzyme and the molecular docking studies demonstrated that
,
and
exhibited high binding interactions than the parent molecule (ddI) and other derivatives; evaluated the aromatase enzyme inhibition. The cell viability, cell proliferation, lactate dehydrogenase showed potential anti-proliferative in dose dependent manner, these results were well correlated with hoesch stain and DNA fragmentation on MDA-MB-231 breast cancer cell lines. Cytotoxicity results disclosed that tryptophan amino acid ester substituted derivative
showed potential cell death against MDA-MB-231 cancer cell lines. Furthermore, compound
has great potential significance for further investigations (
).
There is a rising demand for low-cost, high-information-capacity optical signal processing. The number of devices is limited of performing different Boolean functions using a single unit. In the ...current manuscript, six basic logic gates, including OR, XOR, NAND, AND, NOR, and XNOR, are implemented in a single unit utilizing all-optical silicon microring resonator. At first, three microring resonators are used to get the AND, XOR and NOR logic functions. Then, beam combiners are used to get the OR, NAND and XNOR functions from AND, XOR, and NOR functions. In MATLAB, the suggested design is numerically simulated to verify the functions at an operational speed of nearly 260 Gbps. The required pump power for switching is only 1.95 mW for microring resonator based switch which is very less comparatively. Also, some performance parameters like “extinction ratio”, “contrast ratio”, “amplitude modulation”, “on–off ratio”, and “quality factor” are evaluated. To design the circuit practically, optimized parameters of the circuits have been selected. The obtained values of “extinction ratio” and “contrast ratio” are 14.97 dB and 19.03 dB, respectively. The value of AM is 0.17 dB which is less than 1 dB. The on–off ratio of the MRR is 35.10 dB which is much higher than expected.
In flip-chip design, voltage drop reduction in the power ground network has become a challenging problem particularly in the modern Multiple Supply Voltage(MSV) designs. An effective P/G network ...design and floorplanning- based solutions helps to produce a quality power plan in the layout. Hence, this paper proposes an iterative MSV floorplanning methodology that performs modifications in the existing floorplan representation that satisfies the voltage island constraint and produce an IR drop-aware quality layout. Furthermore, the proposed methodology is integrated with commercial tool design flow to analyze the reduction of IR drop in the layout. Two simulation-based experiments are performed in this paper to showcase the significance of this work. Firstly, it presents the simulation results that benchmark the proposed idealogy in non-flip chip designs. Secondly, the presented framework is integrated in flip-chip layouts of FIR design operating with two voltage islands for low power consumption. To understand the ability of the proposed floorplanning approach, the simulation were performed for two different sized P/G mesh structure for various mesh width. Experimental results from both simulations demonstrate that the proposed MSV floorplanning technique is effective in reducing IR drop while optimizing the design for low power dissipation.
Polyester-based hybrid composites were developed by combining the tamarind fruit (Tf) and glass fibers into a polyester matrix. Hardness, impact strength, frictional coefficient, and chemical ...resistance of hybrid composites with and without alkali treatments were studied. Variation of the aforementioned mechanical properties and chemical resistance was studied with different fiber lengths, such as 1, 2, and 3 cm. A 9 vol% of the tamarind and glass fibers was reinforced into the polyester matrix. The aforementioned mechanical properties were optimally improved at 2-cm fiber length when compared with 1- and 3-cm fiber lengths. Chemical resistance was also significantly improved for all chemicals except toluene. A 3°C rise in decomposition temperature while a 2°C rise in glass transition temperature was observed from TGA and DSC micrograms, respectively.
Celotno besedilo
Dostopno za:
BFBNIB, DOBA, GIS, IJS, IZUM, KILJ, KISLJ, NUK, PILJ, PNG, SAZU, UILJ, UKNU, UL, UM, UPUK
The paper presents a bit-level chaos based color image encryption technique using Logistic-Sine-Tent-Chebyshev (LSTC) map. The color image is first decomposed into red, blue, and green color image ...components. Each color image component is transformed to an 8-bit binary plane. Mutual diffusion of two sequences is used to scramble two binary elements using the LSTC map, cyclic shifts, and the XOR operation. The binary element confusion is performed using a chaos map and transformed into binary bit planes. With the help of the chaos map, the binary element is swapped and transformed into another binary bit plane. Individual cipher text image components are obtained by combining the binary bit planes. Finally, the encrypted image component is combined to generate the color cipher text image. The proposed scheme experimental results show excellent resistance to statistical attack, differential attack, and brute-force attack with a single round of encryption. As a result, the proposed scheme is secure and reliable for transmitting color images over the internet.
•This paper is proposed with modified full-search block motion estimation algorithm for different video coding standard.•The proposed architecture for full-search block motion estimation allows the ...frames into nine 16 X 16 sub-blocks.•And finite-state machine is integrated with the proposed architecture for best block matching in the search area.•The proposed algorithm was designed using Verilog HDL and implemented in Altera FPGA using Altera Quartus II synthesis tool.
Due to the increasing demand of data transfer in video process. Motion estimation is an important component in power-consumption of video codec. And the important thing to design the motion estimation is power optimization, which is achieved by carefully designing motion estimator. This paper is proposed with modified full-search block motion estimation algorithm for different video coding standard. The proposed architecture for full-search block motion estimation allows the frames into nine 16X16 sub-blocks. And finite-state machine is integrated with the proposed architecture for best block matching in the search area. In the proposed architecture, cells are used to store the current frame and compare the current frame with a reference frame to achieve the low-power by reusing the block. The proposed algorithm was designed using Verilog HDL and implemented in Altera FPGA using Altera Quartus II synthesis tool. Compare with the conventional architecture, our proposed architecture was designed with low power and area and high Peak signal to noise ratio (PSNR), which is 5 times faster than the conventional method.
