In order to apply power electronics systems to applications such as superconducting systems under cryogenic temperatures, it is necessary to investigate the characteristics of different parts in the ...power electronics system. This article reviews the influence of cryogenic temperature on power semiconductor devices including Si and wide bandgap switches, integrated circuits, passive components, interconnection and dielectric materials, and some typical cryogenic converter systems. Also, the basic theories and principles are given to explain the trends for different aspects of cryogenically cooled converters. Based on the review, Si active power devices, bulk Complementary metal-oxide-semiconductor (CMOS) based integrated circuits, nanocrystalline and amorphous magnetic cores, NP0 ceramic and film capacitors, thin/metal film and wirewound resistors are the components suitable for cryogenic operation. Pb-rich PbSn solder or In solder, classic printed circuit boards material, most insulation papers and epoxy encapsulant are good interconnection and dielectric parts for cryogenic temperatures.
In a phase-leg configuration, the high-switching-speed performance of silicon carbide (SiC) devices is limited by the interaction between the upper and lower devices during the switching transient ...(crosstalk), leading to additional switching losses and overstress of the power devices. To utilize the full potential of fast SiC devices, this paper proposes two gate assist circuits to actively suppress crosstalk on the basis of the intrinsic properties of SiC power devices. One gate assist circuit employs an auxiliary transistor in series with a capacitor to mitigate crosstalk by gate loop impedance reduction. The other gate assist circuit consists of two auxiliary transistors with a diode to actively control the gate voltage for crosstalk elimination. Based on CREE CMF20120D SiC MOSFETs, the experimental results show that both active gate drivers are effective to suppress crosstalk, enabling turn-on switching losses reduction by up to 17%, and negative spurious gate voltage minimization without the penalty of decreasing the switching speed. Furthermore, both gate assist circuits, even without a negative isolated power supply, are more effective in improving the switching behavior of SiC devices in comparison to the conventional gate driver with a -2 V turn-off gate voltage. Accordingly, the proposed active gate assist circuits are simple, efficient, and cost-effective solutions for crosstalk suppression.
The double pulse test (DPT) is a widely accepted method to evaluate the dynamic behavior of power devices. Considering the high switching-speed capability of wide band-gap devices, the test results ...are very sensitive to the alignment of voltage and current (V-I) measurements. Also, because of the shoot-through current induced by C dv/dt (i.e., cross-talk), the switching losses of the nonoperating switch device in a phase-leg must be considered in addition to the operating device. This paper summarizes the key issues of the DPT, including components and layout design, measurement considerations, grounding effects, and data processing. Additionally, a practical method is proposed for phase-leg switching loss evaluation by calculating the difference between the input energy supplied by a dc capacitor and the output energy stored in a load inductor. Based on a phase-leg power module built with 1200-V/50-A SiC MOSFETs, the test results show that this method can accurately evaluate the switching loss of both the upper and lower switches by detecting only one switching current and voltage, and it is immune to V-I timing misalignment errors.
Overcurrent protection of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) remains a challenge due to lack of practical knowledge. This paper presents three ...overcurrent protection methods to improve the reliability and overall cost of SiC MOSFET-based converters. First, a solid-state circuit breaker (SSCB) composed primarily by a Si IGBT and a commercial gate driver IC is connected in series with the dc bus to detect and clear overcurrent faults. Second, the desaturation technique using a sensing diode to detect the drain-source voltage under overcurrent faults is implemented as well. Third, a novel active overcurrent protection scheme through dynamic evaluation of fault current level is proposed. The design considerations and potential issues of the protection methods are described and analyzed in detail. A phase-leg configuration-based step-down converter is built to evaluate the performance of the protection schemes under various conditions, considering variation of fault type, decoupling capacitance, protection circuit parameters, etc. Finally, a comparison is made in terms of fault response time, temperature-dependent characteristics, and applications to help designers select a proper protection method.
Double pulse test (DPT) is a widely accepted method to evaluate the switching characteristics of semiconductor switches, including SiC devices. However, the observed switching performance of SiC ...devices in a PWM inverter for induction motor drives is almost always worse than the DPT characterization, with slower switching speed, more switching losses, and more serious parasitic ringing. This paper systematically investigates the factors that limit the SiC switching performance from both the motor side and inverter side, including the load characteristics of induction motor and power cable, two more phase legs for the three-phase PWM inverter in comparison with the DPT, and the parasitic capacitive coupling effect between power devices and heat sink. Based on a three-phase PWM inverter with 1200 V SiC MOSFETs, test results show that the induction motor, especially with a relatively long power cable, will significantly impact the switching performance, leading to a switching time increase by a factor of 2, switching loss increase up to 30% in comparison with that yielded from DPT, and serious parasitic ringing with 1.5 μs duration, which is more than 50 times of the corresponding switching time. In addition, the interactions among the three phase legs cannot be ignored unless the decoupling capacitors are mounted close to each phase leg to support the dc bus voltage during switching transients. Also, the coupling capacitance due to the heat sink equivalently increases the junction capacitance of power devices; however, its influence on the switching behavior in the motor drives is small considering the relatively large capacitance of the motor load.
Newly emerged gallium nitride (GaN) devices feature ultrafast switching speed and low on-state resistance that potentially provide significant improvements for power converters. This paper ...investigates the benefits of GaN devices in an LLC resonant converter and quantitatively evaluates GaN devices' capabilities to improve converter efficiency. First, the relationship of device and converter design parameters to the device loss is established based on an analytical model of LLC resonant converter operating at the resonance. Due to the low effective output capacitance of GaN devices, the GaN-based design demonstrates about 50% device loss reduction compared with the Si-based design. Second, a new perspective on the extra transformer winding loss due to the asymmetrical primary-side and secondary-side current is proposed. The device and design parameters are tied to the winding loss based on the winding loss model in the finite element analysis (FEA) simulation. Compared with the Si-based design, the winding loss is reduced by 18% in the GaN-based design. Finally, in order to verify the GaN device benefits experimentally, 400- to 12-V, 300-W, 1-MHz GaN-based and Si-based LLC resonant converter prototypes are built and tested. One percent efficiency improvement, which is 24.8% loss reduction, is achieved in the GaN-based converter.
This paper presents an active gate driver (AGD) for IGBT modules to improve their overall performance under normal condition as well as fault condition. Specifically, during normal switching ...transients, a di/dt feedback controlled current source and current sink is introduced together with a push-pull buffer for dynamic gate current control. Compared to a conventional gate drive strategy, the proposed one has the capability of reducing the switching loss, delay time, and Miller plateau duration during turn-on and turn-off transient without sacrificing current and voltage stress. Under overcurrent condition, it provides a fast protection function for IGBT modules based on the evaluation of fault current level through the di/dt feedback signal. Moreover, the AGD features flexible protection modes, which overcomes the interruption of converter operation in the event of momentary short circuits. A step-down converter is built to evaluate the performance of the proposed driving schemes under various conditions, considering variation of turn-on/off gate resistance, current levels, and short-circuit fault types. Experimental results and detailed analysis are presented to verify the feasibility of the proposed approach.
This paper presents a comprehensive short-circuit ruggedness evaluation and numerical investigation of up-to-date commercial silicon carbide (SiC) MOSFETs. The short-circuit capability of three types ...of commercial 1200-V SiC MOSFETs is tested under various conditions, with case temperatures from 25 to 200 °C and dc bus voltages from 400 to 750 V. It is found that the commercial SiC MOSFETs can withstand short-circuit current for only several microseconds with a dc bus voltage of 750 V and case temperature of 200 °C. The experimental short-circuit behaviors are compared, and analyzed through numerical thermal dynamic simulation. Specifically, an electrothermal model is built to estimate the device internal temperature distribution, considering the temperature-dependent thermal properties of SiC material. Based on the temperature information, a leakage current model is derived to calculate the main leakage current components (i.e., thermal, diffusion, and avalanche generation currents). Numerical results show that the short-circuit failure mechanisms of SiC MOSFETs can be thermal generation current induced thermal runaway or high-temperature-related gate oxide damage.
Junction temperature is an important design/operation parameter, as well as, a significant indicator of device's health condition for power electronics converters. Compared to its silicon (Si) ...counterparts, it is more critical for silicon carbide (SiC) devices due to the reliability concern introduced by the immaturity of new material and packaging. This paper proposes a practical implementation using an intelligent gate drive for online junction temperature monitoring of SiC devices based on turn-off delay time as the thermo-sensitive electrical parameter. First, the sensitivity of turn-off delay time on the junction temperature for fast switching SiC devices is analyzed. A gate impedance regulation assist circuit is proposed to enhance the sensitivity by a factor of 60 and approach 736 ps/°C tested in the case study with little penalty on the power conversion performance. Next, an online monitoring unit based on gate assist circuits is developed to monitor the turn-off delay time in real time with the resolution less than 104 ps. As a result, the micro-controller is capable of "reading" junction temperature during the converter operation. Finally, a SiC-based half-bridge inverter is constructed with an intelligent gate drive consisting of the gate impedance regulation circuit and online turn-off delay time monitoring unit. Experimental results demonstrate the feasibility and accuracy of the proposed approach.
Paralleling three phase three-level inverters is gaining popularity in industrial applications. However, analytical models for the harmonics calculation of a three-level neutral point clamped (NPC) ...inverter with popular space vector modulation (SVM) are not found in the literature. Moreover, how interleaving angle impacts the dc- and ac-side harmonics and electromagnetic interference (EMI) harmonics in parallel interleaved three-level inverters and how to optimize interleaving angle to reduce these harmonics have not been discussed in the literature. Furthering previous study, this article presents the modeling, analysis, and reduction of harmonics in paralleled and interleaved three-level NPC inverters with SVM. Analytical models for harmonic calculation are developed, and the dc-side harmonics characteristics of an NPC inverter are identified. The impact of interleaving angle on the ac-side voltage and dc-link current harmonics of parallel interleaved three-level NPC inverters is comprehensively studied. The impact of switching frequency and interleaving angle on EMI harmonics is also illustrated. Optimal interleaving angle ranges to reduce these harmonics are derived analytically. The developed models and harmonic reduction analysis are verified experimentally with two paralleled and interleaved three-level NPC inverters.
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