A total of one hundred and nine accessions of cultivated holy basil (Ocimum tenuiflorum L.) germplasm, representing different phyto-geographical regions of India were investigated for morphological ...characterization. Data were recorded on 32 descriptor traits (both qualitative and quantitative) using the minimal descriptors developed by the ICAR-National Bureau of Plant Genetic Resources, with minor modifications. Analysis of the data was carried out using Ward’s Minimum Variance method and categorized into seven major clusters. PCA analysis revealed that the first six principal components (Eigen value greater than 1), are contributing 72.33% of the total variance which were mostly influenced by mature leaf length, leaf width, leaf petiole length, plant height, seed length, seed width, days to flower initiation, essential oil percentage, seed length/width ratio, leaf length/width ratio, number of primary branches and fresh herbage yield. All the accessions showed high degree of variation, indicating rich morphological diversity within the population.
Universal Pattern Set for Arithmetic Circuits Kumar, Ashok; Choudhary, Rahul Raj; Bhardwaj, Pooja ...
International journal of computer applications,
01/2012, Letnik:
40, Številka:
15
Journal Article
Odprti dostop
The exponential increase in test cost is one of the new challenges being posed by technology scaling. This Paper has been aimed to deal with the issue of testing cost which adds to the chip cost. ...Here we propose a new pattern set for testing the arithmetic circuits which contains a minimum number of test vectors and easy to generate on the chip and hence supports at-speed testing of the circuit. Though maximum fault coverage is desired but practically generation of test vectors for testing of all the possible defects is not at all feasible. This leads to the modeling of defects as faults which facilitate for simplification of test generation process. Though various fault models have been proposed, the single stuck-at fault model is one of widely accepted model because of having closeness to the actual defects and also, it provide the algorithmic possibilities which, further helps in generation of test vectors. The desired smaller DPM (defective parts per million) levels for devices, creates the need for application of better fault models, which can model the defects in the most accurate fashion. This result in complex fault models which tends to make test generation tedious or even impossible and ultimately increase the test cost. Our motive is to cut down the test cost by finding the minimal number of test vectors for the test. If reduction in the patterns for one module is achieved, it would reduce the overall test cost. We propose universal pattern set which gives good fault coverage for arithmetic circuit with small set of vectors.
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