Abstract
The Zero Degree Calorimeters (ZDC) were designed to provide the measurement of the event geometry and luminosity in heavy-ion operation. The readout system was redesigned in order to operate ...in continuous mode without dead time at 2.5 MHz event rate. The new acquisition chain is based on a commercial 12 bit digitizer with a sampling rate of about 1 GSps, assembled on an FPGA Mezzanine Card. The signals produced by the 26 ZDC channels are digitized, and samples are processed through an FPGA to extract information such as timing, baseline average estimation and luminosity.
The ALICE Zero Degree Calorimeters (ZDC) provide information about event geometry in heavy-ion collisions through the detection of spectator nucleons and allow to estimate the delivered luminosity. ...They are also very useful in p–A collisions, allowing an unbiased estimation of collision centrality. The Run 3 operating conditions will involve a tenfold increase in instantaneous luminosity in heavy-ion collisions, with event rates that, taking into account the different processes, could reach 5 MHz in the ZDCs. The challenges posed by this demanding environment lead to a redesign of the readout system and to the transition to a continuous acquisition. The new system is based on 12 bit, 1 Gsps FMC digitizers that will continuously sample the 26 ZDC channels. Triggering, pedestal estimation and luminosity measurements will be performed on FPGA directly connected to the front-end. The new readout system and the performances foreseen in Run 3 are presented.
Abstract
The ToASt ASIC is a 64 channel integrated circuit designed for the readout of the double-sided silicon strip sensors that will equip the micro-vertex detector of the PANDA experiment. The ...ToASt ASIC operates with a 160 MHz clock, which defines also the time resolution. A common time stamp is distributed to all channels to provide a common time reference for time of arrival and time over threshold measurements. Two 160 Mb/s serial lines provide the interface to the data concentrator. ToASt is implemented in a commercial 110 nm CMOS technology with triplicated logic to protect against single event upsets.
The upgrade of the acquisition for the muon Drift Tube foresees the relocation of the Sector Collector electronics, from the cavern towards the counting room. The project requires an electrical to ...optical conversion by the Copper to Optical Fibre (CUOF) board, developed and tested in a radiation environment for components qualification. More tests were performed inserting the prototype in the actual acquisition system, with such a good result that a substantial production is in progress. The installation for a large number of channels is planned for the 2013 autumn, with the new system that will be active beside the actual one.
ToPiX v4 is the prototype for the readout of the silicon pixel sensors for the Micro Vertex Detector of the PANDA experiment. ToPiX provides position, time and energy measurement of the incoming ...particles and is designed for the triggerless environment foreseen in PANDA. The prototype includes 640 pixels with a size of 100 x 100 mum super(2), a 160 MHz time stamp distribution circuit to measure both particle arrival time and released energy (via ToT technique) and the full control logic. The ASIC is designed in a 0.13 mum CMOS technology with SEU protection techniques for the digital parts.
The ongoing program to develop a custom hybrid pixel detector for the innermost layers of the tracking system of the PANDA experiment foresees thinned epitaxial silicon sensors and pixel readout ...electronics based on 130
nm CMOS technology. The displacement damage test with neutron from the nuclear reactor has been performed on some test structures, characterized by high resistivity epitaxial silicon material, showing annealing effects. Besides, the second reduced scale prototype for the pixel readout has been designed and tested.
Results concerning study of epitaxial silicon devices and characterization of chip using time-over-threshold (TOT) approach will be presented.
The Silicon Pixel Detector (SPD) of the future PANDA experiment is the closest one to the interaction point and therefore the sensor and its electronics are the most exposed to radiation. The Total ...Ionizing Dose (TID) issue has been addressed by the use of a deep-submicron technology (CMOS 0.13 mu m) for the readout ASICs. While this technology is very effective in reducing radiation induced oxide damage, it is also more sensitive to Single Event Upset (SEU) effects due to their extremely reduced dimensions. This problem has to be addressed at the circuit level and generally leads to an area penalty. Several techniques have been proposed in literature with different trade-off between level of protection and cell size. A subset of these techniques has been implemented in the PANDA SPD ToPiX readout ASIC prototypes, ranging from DICE cells to triple redundancy. Two prototypes have been tested with different ion beams at the INFN-LNL facility in order to measure the SEU cross section. Comparative results of the SEU test will be shown, together with an analysis of the SEU tolerance of the various protection schemes and future plans for the SEU protection strategy which will be implemented in the next ToPiX prototype.
The ToPiX ASIC is a custom development for the hybrid pixel sensors of the PANDA experiment Micro Vertex Detector. The ASIC will provide both the time and amplitude informations (via the Time over ...Threshold technique) of the incoming particle. ToPiX will consist of a matrix of 116 x 110 cells with a pixel size of 100 x 100 mm super(2), the column readout logic and two 311 Mbit/s serializers. A reduced scale prototype in CMOS 0.13 mu m has been designed and tested. The prototype includes eight columns with the full cell analogue and digital circuitry and the end of column readout.
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