TANOS Charge Trap Flash Approach (CTF) is a candidate to replace floating gate approach (FG) for sub-32 nm technology node. However the main challenge for TANOS is its poor retention characteristics. ...In this paper, we show that by performing an O 2 anneal after Al 2 O 3 deposition the charge retention is considerably improved as well as the other memory characteristics: program, erase, endurance.
We report for the first time that the optimization of a HfSiON process on Ni-FUSI devices is best tackled using a design of experiments (DOE Myers RH, Montgomery. Response surface methodology. New ...York, DC: Wiley; 1995) approach. We show that a DOE allows for directly linking process parameters to relevant short channel performance metrics. By tuning the SiO
2 thickness, HfSiO thickness, Hf concentration, nitridation parameters and by using response surface modeling (RSM), we report an improvement of 12%/17% in nMOS/pMOS drive current (
I
dsat 600/255
uA/μm at
I
off
=
20
pA/μm and
V
dd
=
1.1
V) over our reference process. In parallel, we demonstrate that by selecting the right parameters, plasma nitridation can outperform thermal nitridation with NH
3. We believe that this new approach will be useful for device engineers and can be easily applied.
When scaling down Floating Gate (FG) based NAND Flash to the 40 nm-technology node and beyond, the main challenge is the electrical interference between adjacent cells. This can be drastically ...reduced by thinning the FG below 20 nm. For the 43 nm-node, 60 nm thick FG layers are already used 1. In this paper we present, based on ASMpsilas Silcore reg precursor for silicon deposition, a proof-of-concept that scaling down the floating gate thickness to 15 nm has no impact on the memory operation.
We report for the first time the demonstration of 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV). The Cu TSV process is inserted between contact and M1 of ...our reference 0.13 mum CMOS process on 200 mm wafers. The top die is thinned down to 25 mum and bonded to the landing wafer by Cu-Cu thermo-compression. Both top and landing wafers contain CMOS finished at M2 to evaluate the process impact both FEOL and BEOL. The results confirm no degradation of the FEOL performance. The functionality of various ring oscillator topologies that include inverters distributed over both top and bottom dies connected through TSVs demonstrates excellent chip integrity after the TSV and 3D stacking process.
A 90nm CMOS technology has been used as the baseline for a low-cost RF-CMOS platform, with improved analog/RF performances of the active and passive devices. The 65 nm gate length NMOS exhibits ...240GHz peak f/sub max/ and 170GHz peak f /sub T/. A peak Q of 40@5GHz is measured for a symmetrical 2.7 nH above-IC inductor. This combination leads to a world record performance of a monolithic 5 GHz RF CMOS low noise amplifier presenting a very high gain of 18dB and very low noise figure of 1.5dB, for only 4.8mW power consumption.
Optimizing and controlling the radiation hardness of a CCD process Wulf, F; Heyns, M; Debenest, P ...
Radecs 91: Radiation : Effects on Components and Systems :First European Conference on Radiation and Its Effects on Devices and Systems : LA Grande,
01/1992
Journal Article
The effect of the post-oxidation annealing temperatures (POA) in the range of 800 degree C to 950 degree C in N sub(2) atmosphere and rapid thermal annealing (RTA) after source/drain implantation on ...the radiation hardness of a typical CCD process have been studied using MOS capacitors and transistors. The prompt and delayed generated/ annealed density of oxide charges and interface states at annealing temperatures of 25 degree C and 100 degree C maintaining the same bias condition used during irradiation have been investigated. Negative bias temperature treatment at 200 degree C and an oxide field of - 5 MV/cm have been performed to control the long-term stability of the different process variations.
The integration of fully silicided gates on a high-k dielectric in a standard process flow offers a solid alternative to the conventional Poly/SiON devices. In this work, we provide an extensive ...analysis of the module yield extracted for such devices highlighting the need for specific additional alarm flags without which some integration problems might be overlooked. The impact at the circuit level is studied and supported by modeling work on simple ring-oscillators.
In this work, we present a methodology for characterizing the impact of circuit layout style, technology elements (low-k material, resist choice), device engineering and temperature on the circuit ...power-delay trade-off. We provide experimental results supported by modeling work, showing significant improvements in circuit speed at fixed power levels resulting from improvements in layout style and technology. For instance, the use of a more advanced resist at gate level leads to a 3/spl times/ reduction in static power dissipation at a given ring-oscillator (RO) delay or in other words close to a 10% improvement in the inverter delay for a similar static power dissipation.
For the first time we demonstrate ultra-thin hybrid floating gate (HFG) planar NVM cell performance and reliability. Results not only confirm the high potential of the HFG thickness scaling down to 4 ...nm with improved program performance, but also show excellent post cycling data retention and P/E cycling endurance. The optimized ultra-thin HFG planar cells show potential for manufacturability and scalability for high density memory application.
A nonvolatile memory structure with hybrid (poly/metal) floating gate in combination with an Al 2 O 3 interpoly dielectric is investigated for sub-20nm scaling. Floating gate thickness scaling down ...to only 5nm with excellent program/erase performance and reliability is demonstrated to address the issue of increased cell-to-cell interference. It is further shown that a hybrid floating gate also offers great benefit when used in combination with ONO, which still is the conventional interpoly dielectric layer used in state-of-the-art floating gate Flash memories.
