A vertical cylindrical SONOS cell with a novel bilayer polysilicon channel down to 22-nm diameter for 3-D NAND Flash memory is successfully developed. We introduce a thin amorphous silicon layer ...along with the oxide-nitride-oxide (ONO) gate stack inside the memory hole. This silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole, after which it serves as the first layer of the bilayer polysilicon channel. This approach enables the 3-D architecture to achieve minimum cell area (4 F 2 , with F being the feature size) without the need for the so-called pipeline connections. The smallest functional cells have the memory hole diameter F = 45 nm, resulting in 22-nm channel diameter. In case 16 cells are stacked, F = 45 nm would correspond to an equivalent 11-nm planar cell technology node. Excellent program/erase and retention obtained with the all-deposited ONO stack are demonstrated.
The hybrid floating gate (FG) concept, previously demonstrated in FG capacitors, has been proven in fully integrated stacked memory cells. Results not only confirm the high potential of the concept ...in terms of improved program performance, but also show excellent data retention and program/erase cycling endurance. Key for achieving this result has been the optimization of the sidewall and spacer processing. Hybrid FG cells are therefore a viable solution to extend the nand Flash memory roadmap below the 20-nm technology node.
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► SiO
2/Si
3N
4/SiO
2 (ONO) gate stack thickness/recipes optimization towards 3D SONOS memory cell optimization. ► Investigation of the influence of different polysilicon substrates ...influence on memory operation. ► Use of Fully Silicided gate (FUSI) for erase improvement.
A planar SONOS capacitor was used to optimize different parameters of the gate stack, in view of integration in a 3D cell. It is found that a poly-Si substrate strongly degrades the channel mobility but program and retention are not compromised. The ONO stack is found to scale down to 3/4/5
nm for tunnel oxide/trapping nitride/blocking oxide, respectively. FUSI gate could be an interesting option to improve the erase operation.
In this paper, we provide evaluation of memory stacks with La, Lu and Gd aluminates as charge trapping materials. Critical integration issues are pointed out, particularly the mixing of these ...materials with adjacent layers. It is found that, in order to control the mixing of the aluminates with the tunnel oxide, nitride (for Gd) or nitride+oxide (for La and Lu) buffer layers have to be used. The nitride buffer layer, however, mixes with the tunnel oxide during stack fabrication. This results in very good erase and endurance performance, which is attributed to enhanced hole tunneling from the Si substrate, but degrades the retention performance.
A comparative study of the growth behavior of nm-thin ruthenium layers by plasma enhanced atomic layer deposition using two ruthenium precursors is discussed. For bis(ethylcyclopentadienyl)-ruthenium ...or Ru(EtCp)2, we have found a large incubation time on titanium nitride when using N2/NH3 plasma. With N2/H2 plasma the incubation was significantly reduced. For (methylcyclopentadienyl-pyrrolyl)ruthenium or MCPRu, no incubation was observed for either plasmas. The measured growth per cycle was ~ 0.02 nm for Ru(EtCp)2 whereas ~ 0.04 nm for MCPRu. The top surface of the PE-ALD Ru films can be oxidized without surface roughening by applying a low pressure O2 anneal, while O3 exposure leads to roughening due to etching and re-deposition downstream of etched Ru. Awareness of the impact of oxidizing ambients on Ru is essential for successful integration of Ru layers as electrode in metal-insulator-metal capacitors.
Rare-Earth aluminates GdAlO and LuAlO are investigated as blocking dielectric for Al 2 O 3 replacement in TANOS flash memory devices. Since the energy bandgap of aluminates strongly depends on their ...crystallization phase and it is the highest for orthorombic phase, both materials were engineered using templates to assure the highest Eg and k-value after crystallization. As a consequence, the memory stack performances are significantly improved. Compared to Al 2 O 3 reference top dielectric, retention can be improved.
3D integration has the potential to alleviate the performance limitations that CMOS scaling is facing provided that it preserves the integrity of both front end and back end devices and constituting ...materials. The impact of wafer thinning and of the proximity of through silicon via on active devices, back end structures, ring oscillators and mixed signal circuit are reported for the first time for a High-k/Metal Gate first strained CMOS technology with low-k BEOL. The relative stress induced by the STI and the TSV are measured by micro-Raman spectroscopy. The measured impact of the stress on a sensitive DAC circuit is used to define a safe keep out area.
The integration of La, Gd, and Lu aluminates in a Charge-Trapping Flash (CTF) memory flow as alternative trapping materials is evaluated. It is found that, in order to control the mixing of the ...aluminates with the tunnel oxide, nitride (for Gd) or nitride + oxide (for La and Lu) buffer layers have to be used. It is also found that during the post-deposition annealing treatments, the nitride buffer layer mixes with the tunnel oxide. This results in very good erase and endurance performance, which is attributed to enhanced hole tunneling from the Si substrate.
This work provides for the first time comprehensive and early guidelines for TSV integration in 10nm node bulk FinFET technology. The key contributors to the TSV proximity induced Keep Out Zone (KOZ) ...for FinFET devices are analyzed. Advanced TCAD sub-band modeling of the stress impact on the carrier transport is verified by uniaxial wafer bending experiments. This work provides an analytic compact model to derive first KOZ guidelines for scaled FinFET technologies, introducing the KOZ figure of merit K that directly links to KOZ length and area.
