The Silicon Vertex Trigger (SVT) provides the CDF experiment with a powerful tool for fast and precise track finding and fitting at trigger level. The system enhances the experiment's reach on ...B-physics and large
P
T
-physics coupled to b quarks. We review the main design features and the performance of the SVT with particular attention to the recent upgrade that improved its capabilities. Finally, we will focus on additional improvements of the functionality of such a system in a more general experimental context.
Medical image processing using brain emulation Sotiropoulou, C.-L; Luciano, P.; Gkaittzis, S. ...
2016 IEEE Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop (NSS/MIC/RTSD),
2016-Oct.
Conference Proceeding
A high performance implementation of an algorithm based on the learning process of the human vision as an edge-enhancing filter for medical images is proposed. It is based on a cognitive image ...processing algorithm that emulates the contour identification process that is believed to be used by the human brain. The algorithm is implemented on an innovative and high performance embedded system for real-time pattern matching. The system design uses Field Programmable Gate Arrays (FPGAs) and the powerful Associative Memory chip (an ASIC) to achieve real-time performance. We present the first results of the algorithm as a 3-D edge detection filter using Magnetic Resonance Images (MRI).
In this paper we propose highly parallel dedicated processors, able to provide precise on-line track reconstruction for future hadronic collider experiments. The processors, organized in a 2-level ...pipelined architecture, execute very fast algorithms based on the use of a large bank of pre-stored patterns of trajectory points. An associative memory implements the first stage by recognizing track candidates at low resolution to match the demanding task of tracking at the detector readout rate. Alternative technological implementations for the associative memory are compared. The second stage receives track candidates and high resolution hits to refine pattern recognition at the associative memory output rate. A parallel and pipelined hardware implements a binary search strategy inside a hierarchically structured pattern bank, stored in high density commercial RAMs.
We present a device, based on the concept of associative memory for pattern recognition, dedicated to on-line track finding in high-energy physics experiments. A large pattern bank, describing all ...possible tracks, can be organized into Field Programmable Gate Arrays where all patterns are compared in parallel to data coming from the detector during readout. Patterns, recognized among 2/sup 66/ possible combinations, are output in a few 30 MHz clock cycles. Programmability results in a flexible, simple architecture and it allows to keep up smoothly with technology improvements. A 64 PAM array has been assembled on a prototype VME board and fully tested up to 30 MHz.
The CDF trigger silicon vertex tracker (SVT) Belforte, S.; Dell'Orso, M.; Donati, S. ...
IEEE transactions on nuclear science,
08/1995, Letnik:
42, Številka:
4
Journal Article, Conference Proceeding
Recenzirano
The design is presented for a device presently being built to perform on line track finding and reconstruction for the CDF (Collider Detector at Fermilab) Silicon Vertex Detector (120 k channels). ...This device will provide track impact parameter information for the CDF Level 2 trigger decision, thus allowing CDF to trigger on events containing a long lived particle, in particular a b-quark. It will be the first device with such a capability installed at a proton-antiproton collider. The capability to separate b decays early in the trigger process is vital to the CDF program to collect a high statistic b sample to attack the study of CP violation in the b sector. Moreover SVT will open access to non-leptonic b decays like B/spl rarr//spl pi//spl pi/.< >
The SVT Hit Buffer Belforte, S.; Dell'Orso, M.; Donati, S. ...
IEEE transactions on nuclear science,
06/1996, Letnik:
43, Številka:
3
Journal Article
Recenzirano
The Hit Buffer is part of the Silicon Vertex Tracker 1, a trigger processor dedicated to the reconstruction of particle trajectories in the Silicon Vertex Detector 2 and the Central Tracking Chamber ...of the Collider Detector at Fermilab. The Hit Buffer is a high speed data-traffic node, where thousands of words are received in arbitrary order and simultaneously organised in an internal structured data base, to be later promptly retrieved and delivered in response to specific requests. The Hit Buffer is capable to process data at a rate of 25 MHz, thanks to the use of special fast devices like Cache-Tag RAMs and high performance Erasable Programmable Logic Devices from the XILINX XC7300 family.
We propose precise and fast-track reconstruction at hadron collider experiments, for use in online trigger decisions. We describe the features of fast-track (FTK), a highly parallel processor ...dedicated to the efficient execution of a fast-tracking algorithm. The hardware-dedicated structure optimizes speed and size; these parameters are evaluated for the ATLAS experiment. We discuss some applications of high-quality tracks available to the trigger logic at an early stage, by using the LHC environment as a benchmark. The most interesting application is online selection of b-quarks down to very low transverse momentum, providing interesting hadronic samples: examples are Z/sup 0/spl rarr//bb~, potentially useful for jet calibration, and multi-b final states for supersymmetric Higgs searches. The paper is generated from outside the ATLAS experiment and has not been discussed by the ATLAS collaboration.
Perspectives for precise and fast track reconstruction in future hadron collider experiments are addressed. We discuss the feasibility of a pipelined highly parallel processor dedicated to the ...implementation of a very fast tracking algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points, called patterns, for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at an input rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution tracks with transverse momentum above a few GeV and search for secondary vertices within typical level-2 times.
The online silicon vertex tracker (SVT) is the new trigger processor dedicated to the two-dimensional (2-D) reconstruction of charged particle trajectories at the Level 2 of the Collider Detector at ...Fermilab (CDF) trigger. The SVT links the digitized pulse heights found within the silicon vertex detector to the tracks reconstructed in the central outer tracker by the Level 1 fast-track finder. Preliminary tests of the system took place during the October 2000 commissioning run of the Tevatron Collider. During the April-October 2001 data taking, it was possible to evaluate the performance of the system. In this paper, we review the tracking algorithms implemented in the SVT and we report on the performance achieved during the early phase of run II.
The Merger board is part of the Silicon Vertex Tracker (SVT), a device dedicated to perform real-time track reconstruction with offline-like resolution and high efficiency at the Level 2 trigger of ...the CDF experiment. The Merger is a custom 9U /spl times/ 400 mm VME board, running at an internal clock frequency of 33 MHz. Its main functional task in SVT is to merge up to four independent data streams into a single one. The merging operation can be performed on a first come, first served basis or according to an ordered sequence. There are four input streams and two identical output streams, so that the Merger also serves as a data fanout function. The board implements detailed error handling and sophisticated data monitoring that make it possible to trace back misfunctioning both in the Merger and in other parts of SVT. Furthermore, the Merger has special modes of operation that can be selected for test and diagnostic purposes. In these working modes, the Merger is a powerful tool that allows one to test other SVT boards at their maximum operating frequency.
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