The linear front-end is the analog processor chosen for the final integration into the pixel readout chip for the high-luminosity upgrade of the CMS experiment at the large hadron collider. The ...front-end has been included in the RD53A chip, designed by the CERN RD53 collaboration and submitted in 2017. An optimized version of the front-end has been designed, submitted, and tested in the framework of the RD53B developments. The optimization is mainly concerned with the time-walk performance of the front-end and with its threshold tuning capabilities. The article describes in detail such design improvements together with the results from the characterization of a small prototype chip including a 16 <inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> 16 pixel matrix featuring both the RD53A and RD53B versions of the front-end. Test results show a significant reduction, about 10 ns for input signals close to the threshold, of the time-walk in the RD53B front-end, featuring a threshold dispersion smaller than 65 electrons r.m.s. after exposure to a total ionizing dose of 1 Grad of X-rays.
The ALICE Zero Degree Calorimeters (ZDC) provide information about event geometry in heavy-ion collisions through the detection of spectator nucleons and allow to estimate the delivered luminosity. ...They are also very useful in p–A collisions, allowing an unbiased estimation of collision centrality. The Run 3 operating conditions will involve a tenfold increase in instantaneous luminosity in heavy-ion collisions, with event rates that, taking into account the different processes, could reach 5 MHz in the ZDCs. The challenges posed by this demanding environment lead to a redesign of the readout system and to the transition to a continuous acquisition. The new system is based on 12 bit, 1 Gsps FMC digitizers that will continuously sample the 26 ZDC channels. Triggering, pedestal estimation and luminosity measurements will be performed on FPGA directly connected to the front-end. The new readout system and the performances foreseen in Run 3 are presented.
Abstract
The readout electronics for the CMS electromagnetic calorimeter is undergoing a re-design in order to cope with the LHC ugrade. In particular, a fourfold increase in the sampling frequency ...(from 40 to 160 MS/s) is required. Therefore a new readout ASIC has been developed. The ASIC, named LiTE-DTU, is designed in a CMOS 65 nm technology. The LiTE-DTU embeds two 12 bit, 160 MS/s ADCs, a time window based sample selection, lossless data compression and 1.28 Gb/s serialization. An on-chip PLL provides the 1.28 GHz clock required by the ADCs and the serializers from the 160 MHz clock.
The development of Low-Gain Avalanche Detectors has opened up the possibility of manufacturing silicon detectors with signal larger than that of traditional sensors. In this paper we explore the ...timing performance of Low-Gain Avalanche Detectors, and in particular we demonstrate the possibility of obtaining ultra-fast silicon detector with time resolution of less than 20 picosecond.
The Gigatracker (GTK) is a hybrid silicon pixel detector designed for the NA62 experiment at CERN. The beam spectrometer, made of three GTK stations, has to sustain high and non-uniform particle rate ...(∼1GHz in total) and measure momentum and angles of each beam track with a combined time resolution of 150ps. In order to reduce multiple scattering and hadronic interactions of beam particles, the material budget of a single GTK station has been fixed to 0.5% X0. The expected fluence for 100 days of running is 2×1014 1MeVneq/cm2, comparable to the one foreseen in the inner trackers of LHC detectors during 10 years of operation. To comply with these requirements, an efficient and very low-mass (<0.15%X0) cooling system is being constructed, using a novel microchannel cooling silicon plate. Two complementary read-out architectures have been produced as small-scale prototypes: one is based on a Time-over-Threshold circuit followed by a TDC shared by a group of pixels, while the other makes use of a constant-fraction discriminator followed by an on-pixel TDC. The read-out ASICs are produced in 130nm IBM CMOS technology and will be thinned down to 100μm or less. An overview of the Gigatracker detector system will be presented. Experimental results from laboratory and beam tests of prototype bump-bonded assemblies will be described as well. These results show a time resolution of about 170ps for single hits from minimum ionizing particles, using 200μm thick silicon sensors.
This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64x64 matrix of 50x50mum super(2) pixels is realised. A digital ...architecture has been developed, with particle efficiency above 99.5% at 3 GHz/cm super(2) pixel rate, trigger frequency of 1 MHz and 12.5musec latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision, analog dead-time below 1%. The chip integrates for the first time many of the components developed by the collaboration in the past, including the Digital-to-Analog converters, Bandgap reference, Serializer, sLVS drivers, and analog Front Ends. Irradiation tests on these components proved their reliability up to 600 Mrad.
A 130 nm ASIC prototype for the NA62 Gigatracker readout Dellacasa, G.; Garbolino, S.; Marchetto, F. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
09/2011, Letnik:
650, Številka:
1
Journal Article
Recenzirano
One of the most challenging detectors of the NA62 experiment is the silicon tracker, called Gigatracker. It consists of three hybrid silicon pixel stations, each one covering an area of 27
mm×60
mm. ...While the maximum pixel size is fairly large,
300
μ
m
×
300
μ
m
the system has to sustain a very high particle rate, 1.5
MHz/mm
2, which corresponds to 800
MHz for each station. To obtain an efficient tracking with such a high rate the required track timing resolution is 150
ps (rms). Therefore the front-end ASIC should provide for each pixel a 200
ps time measurement capability, thus leading to the requirement of time walk compensation and very compact TDCs. Moreover, Single Event Upset protection has to be implemented in order to protect the digital circuitry. An ASIC prototype has been realized in CMOS 130
nm technology, containing three pixel columns. The chip performs the time walk compensation by a Constant Fraction Discriminator circuit, while the time measurement is performed by a Time to Amplitude Converter based TDC, both of them implemented on each pixel cell. The End of Column circuit containing only digital logic is responsible for the data readout from the pixel cell. The whole chip works with a system clock of 160
MHz and the digital logic is SEU protected by the use of Hamming codes. The detailed architecture of the ASIC prototype and test results are presented.
The cross sections of forward emission of one, two and three neutrons by 158A GeV 115In nuclei in collisions with Al, Cu, Sn and Pb targets are reported. The measurements were performed in the ...framework of the ALICE–LUMI experiment at the SPS facility at CERN. Various corrections accounting for the absorption of beam nuclei and produced neutrons in target material and surrounding air were introduced. The corrected cross section data are compared with the predictions of the RELDIS model for electromagnetic fragmentation of 115In in ultraperipheral collisions, as well as with the results of the abrasion–ablation model for neutron emission in hadronic interactions. The measured neutron emission cross sections well agree with the RELDIS results, with the exception of In–Al collisions where the measured cross sections are larger compared to RELDIS. This is attributed to a relatively large contribution of hadronic fragmentation of In on Al target with respect to electromagnetic fragmentation, in contrast to similar measurements performed earlier with 30A GeV 208Pb colliding with Al.
The Gigatracker is a hybrid silicon pixel detector developed to track the highly intense NA62 hadron beam with a time resolution of 150
ps (rms). The beam spectrometer of the experiment is composed ...of three Gigatracker stations installed in vacuum in order to precisely measure momentum, time and direction of every traversing particle. Precise tracking demands a very low mass of the detector assembly (
<
0.5
%
X
0 per station) in order to limit multiple scattering and beam hadronic interactions. The high rate and especially the high timing precision requirements are very demanding: two R&D options are ongoing and the corresponding prototype read-out chips have been recently designed and produced in
0.13
μ
m
CMOS technology. One solution makes use of a constant fraction discriminator and on-pixel analogue-based time-to-digital-converter (TDC); the other comprises a delay-locked loop based TDC placed at the end of each pixel column and a time-over-threshold discriminator with time-walk correction technique. The current status of the R&D program is overviewed and results from the prototype read-out chips test are presented.
The Neutron Zero Degree Calorimeter for the ALICE experiment Arnaldi, R.; Chiavassa, E.; Cicalò, C. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
08/2006, Letnik:
564, Številka:
1
Journal Article
Recenzirano
In this paper, we present the performance of the Neutron Zero Degree Calorimeter (ZN) for the ALICE experiment. The ZN is a quartz-fiber spaghetti calorimeter, which will measure the energy of the ...spectator neutrons in heavy ion collisions at the CERN LHC. Its principle of operation is based on the detection of the Cherenkov light produced by the charged particles of the shower in silica optical fibers, embedded in a W-alloy absorber. The detector was tested at CERN SPS using positive hadron and positron beams with momenta ranging from 50 to
150
GeV
/
c
. The response of the calorimeter, the energy resolution, the localizing capability, the signal uniformity and the transverse profile of the detectable hadronic shower are presented.
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