This brief presents direct electrical measurement of active defects in the strong-accumulation region of N-type 4H-SiC MOS capacitors, which corresponds to the strong-inversion region of N-channel ...MOSFETs. The results demonstrate the existence of an active defect in the gate oxide, located very close to the SiC surface, with localized energy levels between 0.13 eV and 0.23 eV above the bottom of the conduction band. The observed spatial and energy localizations indicates that this is a well-defined defect.
This article reports for the first time the electrical properties of fabricated n-3C-SiC/p-Si heterojunction diodes under external mechanical stress in the 110 direction. An anisotype heterojunction ...diode of n-3C-SiC/p-Si was fabricated by depositing 3C-SiC onto the Si substrate by low-pressure chemical vapor deposition. The mechanical stress significantly affected the scaling current density of the heterojunction. The scaling current density increases with stress and is explained in terms of a band offset reduction at the SiC/Si interface under applied stress. A reduction in the barrier height across the junction owing to applied stress is also explained quantitatively.
The interface properties and electrical characteristics of the n-type 4H-SiC planar and trench metal-oxide-semiconductor （MOS） capacitors are investigated by measuring the capacitance voltage and ...current voltage. The flat-band voltage and interface state density are evaluated by the quasi-static method. It is not effective on further improving the interface properties annealing at 1250 ℃ in NO ambient for above 1 h due to the increasing interface shallow and fast states. These shallow states reduce the effective positive fixed charge density in the oxide. For the vertical MOS capacitors on the （1120） and （1100） faces, the interface state density can be reduced by approximately one order of magnitude, in comparison to the result of the planar MOS capacitors on the （0001） face under the same NO annealing condition. In addition, it is found that Fowler-Nordheim tunneling current occurs at an oxide electric field of 7 MV/cm for the planar MOS device. However, Poole-Frenkel conduction current occurs at a lower electric field of 4 MV/cm for the trench MOS capacitor. This is due to the local field crowded at the trench corner severely causing the electrons to be early captured at or emitted from the SiO2/SiC interface. These results provide a reference for an in-depth understanding of the mobility-limiting factors and long term reliability of the trench and planar SiO2/SiC interfaces.
•The mechanism of negative bias instability in commercial silicon carbide Metal-Oxide-Semiconductor Field-Effect Transistors has been explained through the analysis of transient gate ...currents.•Experimental results demonstrate that near-interface traps with energy levels aligned to the valence band trap holes from the valence band by tunneling.•The transients in the gate current correspond to the trapping of holes by the near-interface traps.•The study demonstrates the impact of the aluminum implantation process on the p-type region, highlighting its role in hole trapping.
This article explains the mechanisms of negative bias instability in commercial n-channel SiC metal–oxide semiconductor field-effect transistors (MOSFETs) by analysis of transient gate currents. The current–voltage measurements were performed at different temperatures along with capacitance–voltage measurements to characterise hole trapping and de-trapping in planar SiC MOSFETs. The experimental results reveal that near-interface traps (NITs) with energy levels aligned to the valence band trap holes from the valence band by tunneling, which is different from published results about NITs with energy levels aligned to the energy gap. The impact of the aluminium implantation process of the p-type region on hole trapping is also demonstrated. The presented analysis also reveals that the hole trapping by NITs is limited to the p-type region, indicating that the aluminium implantation process is responsible for the detected NITs.
The suboptimal performance and low channel-carrier mobility of silicon carbide (SiC) power MOSFETs are attributed to a high density of oxide traps near the 4H-SiC/SiO<inline-formula> <tex-math ...notation="LaTeX">_{\text{2}}</tex-math> </inline-formula> interface. In this article, a commercial 1200-V SiC trench MOSFET has been compared with a planar MOSFET obtained from the same manufacturer. We employed a newly developed integrated-charge method to quantify the near-interface traps (NITs). The results reveal that, at operating gate voltages, 15% of the total channel electrons were trapped for longer than 500 ns in the planar MOSFET compared to 9% in the trench MOSFET.
The popular Tung model for Schottky barrier inhomogeneity considers how low-barrier patches (embedded in a high barrier background) impact the diode current. However, Tung's model fails to account ...for the image-force effect. We analyze how the image force alters the current through an inhomogeneous barrier and find that, in some circumstances, it will smooth the barrier, such that the current will effectively be that of a homogeneous diode. We also show that for a distribution of defect barriers and/or sizes, the diode current can be intermediate between that of a homogeneous diode and a diode dominated by the low-barrier patches. We calculate the parameter values associated with this transitional region. A survey of existing literature applications of Tung's model shows that many diodes are actually operating in this transition region, where Tung's equations are in error. We provide the corrected equations for this case and demonstrate their ability to model practical diode characteristics.
The low channel-carrier mobility in commercial SiC MOSFETs has been attributed to fast electron traps labeled ``NI.'' These traps exhibit anomalous behavior compared to other interface trap signals. ...Furthermore, the electrical parameters extracted from a conventional interface trap analysis of the NI signal are not physically reasonable. To explore the origin of these traps, we fabricated SiC MOS capacitors and measured the conductance across a range of temperatures (between 50 and 300 K). By analyzing the surface electron density at the signal peaks, it is evident that these traps are in fact near-interface traps (NITs)--they are located within the oxide and exchange electrons via a tunneling mechanism. We also developed a model for the conductance generated by NITs and demonstrated a good fit to the experimental data. The knowledge that the NI signal is due to NITs will help in directing future efforts to improve SiC MOSFET performance.
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