Large-scale physics experiments running at high interaction rates place a high demand on the data acquisition system (DAQ) responsible for transporting the data from the detector to the storage. The ...antiProton ANihilation at DArmstadt (PANDA) at the facility for anti-proton and ion research (FAIR) is one such experiment of the future that will not use fixed hardware triggers; instead, the event selection is based on real-time feature extraction, filtering, and high-level correlations. A firmware framework for such real-time data processing has been developed and tested with hardware setup for a PANDA Forward Tracker (FT) prototype. The solution is applicable for other detector subsystems based on the so-called Trigger Readout Board (TRB) data read-out system.
A new design of a detector plane of sub-millimetre thickness for an electromagnetic sampling calorimeter is presented. It is intended to be used in the luminometers LumiCal and BeamCal in future ...linear e
+
e
-
collider experiments. The detector planes were produced utilising novel connectivity scheme technologies. They were installed in a compact prototype of the calorimeter and tested at DESY with an electron beam of energy 1–5 GeV. The performance of a prototype of a compact LumiCal comprising eight detector planes was studied. The effective Molière radius at 5 GeV was determined to be (8.1 ± 0.1 (stat) ± 0.3 (syst)) mm, a value well reproduced by the Monte Carlo (MC) simulation (8.4 ± 0.1) mm. The dependence of the effective Molière radius on the electron energy in the range 1–5 GeV was also studied. Good agreement was obtained between data and MC simulation.
Celotno besedilo
Dostopno za:
DOBA, IZUM, KILJ, NUK, PILJ, PNG, SAZU, SIK, UILJ, UKNU, UL, UM, UPUK
Abstract
For the CMS High Granularity Calorimeter (CE), the final version of the 72-channel front-end ASIC (HGCROC3) was submitted in December 2020. HGCROC3 includes low-noise/high-gain ...preamplifiers/shapers and a 10-bit 40 MHz successive approximation ADC (SAR-ADC) that provide the charge measurement over the linear range of the preamplifier. In the saturation range, a discriminator and a time-to-digital converter (TDC) provide the charge information from the time over threshold (ToT; 200 ns dynamic range, 50 ps binning). A fast discriminator and another TDC provide timing information to 25 ps accuracy. The chip embeds all necessary ancillary services: bandgap circuit, PLL, threshold DACs. We present the experimental results on the latest and final version (HGCROC3) received in April 2021.
Abstract The CMS detector will be upgraded for the HL-LHC to include a MIP Timing Detector (MTD). The MTD will consist of barrel and endcap timing layers, BTL and ETL respectively, providing ...precision timing of charged particles. The BTL sensors are based on LYSO:Ce scintillation crystals coupled to SiPMs with TOFHIR2 ASICs for the front-end readout. A resolution of 30–60 ps for MIP signals at a rate of 2.5 Mhit/s per channel is expected along the HL-LHC lifetime. We present an overview of the TOFHIR2 requirements and design, simulation results and measurements with TOFHIR2 ASICs. The measurements of TOFHIR2 associated to sensor modules were performed in different test setups using internal test pulses or blue and UV laser pulses emulating the signals expected in the experiment. The measurements show a time resolution of 24 ps initially during Beginning of Operation (BoO) and 58 ps at End of Operation (EoO) conditions, matching well the BTL requirements. We also showed that the time resolution is stable up to the highest expected MIP rate. Extensive radiation tests were performed, both with x-rays and heavy ions, showing that TOFHIR2 is not affected by the radiation environment during the experiment lifetime.
The design and measurement results of an ultra-low power multi-channel fast 10-bit Analog-to-Digital Converter (ADC) ASIC, developed for readout systems in future particle physics experiments, are ...discussed. An 8-channel prototype with a PLL-based data serialization and a fast data transmission was designed and fabricated in a 130 nm CMOS process. The ADC converts analog data with sampling rates from about 10 kS/s to 40 MS/s, with power consumption proportional to sampling rate. The resulting Figure of Merit (FOM), for sampling rates 5-40 MS/s, is 35-42 fJ/conv.-step, per ADC channel. Similar power contribution is spent for fast data serialization and the largest contribution goes to data transmission. A wide spectrum of static and dynamic measurements confirm very good performance of this multi-channel ADC with ENOB ~9.2 bits, an excellent channel uniformity, and negligible crosstalk. The ADC works asynchronously and so it is not limited to systems with uniform time sampling. The ADC is designed using dynamic circuitry which eliminates static power consumption (except leakage), as a consequence it is ready for applications requiring power cycling.
The standardization of the calibration of optical sensors in photogrammetry and remote sensing has been discussed for more than a decade. Projects of the German DGPF and the European EuroSDR led to ...the abstract International Technical Specification ISO/TS 19159-1:2014 “Calibration and validation of remote sensing imagery sensors and data – Part 1: Optical sensors”. This article presents the first software interface for a read- and write-access to all metadata elements standardized in the ISO/TS 19159-1. This interface is based on an xml-schema that was automatically derived by ShapeChange from the UML-model of the Specification. The software interface serves two cases. First, the more than 300 standardized metadata elements are stored individually according to the xml-schema. Secondly, the camera manufacturers are using many administrative data that are not a part of the ISO/TS 19159-1. The new software interface provides a mechanism for input, storage, editing, and output of both types of data. Finally, an output channel towards a usual calibration protocol is provided. The interface is written in Java. The article also addresses observations made when analysing the ISO/TS 19159-1 and compiles a list of proposals for maturing the document, i.e. for an updated version of the Specification.
A prototype of a luminometer, designed for a future
e
+
e
-
collider detector, and consisting at present of a four-plane module, was tested in the CERN PS accelerator T9 beam. The objective of this ...beam test was to demonstrate a multi-plane tungsten/silicon operation, to study the development of the electromagnetic shower and to compare it with MC simulations. The Molière radius has been determined to be 24.0 ± 0.6 (stat.) ± 1.5 (syst.) mm using a parametrization of the shower shape. Very good agreement was found between data and a detailed Geant4 simulation.
Celotno besedilo
Dostopno za:
DOBA, IZUM, KILJ, NUK, PILJ, PNG, SAZU, SIK, UILJ, UKNU, UL, UM, UPUK
Abstract
The HKROC ASIC was originally designed to readout the photomultiplier tubes (PMTs) for the Hyper-Kamiokande (HK) experiment. HKROC is a very innovative ASIC capable of readout a large number ...of channels satisfying stringent requirements in terms of noise, speed and dynamic range. Each HKROC channel features a low-noise preamplifier and shapers, a 10-bit successive approximation Analog-to-Digital Converter (SAR-ADC) (designed by AGH Krakow) for the charge measurement (up to 2500 pC) and a Time-to-Digital Converter (TDC) (designed by CEA IRFU group) for the Time-of-Arrival (ToA) measurement with 25 ps binning. HKROC is auto-triggered and includes all necessary ancillary services as bandgap circuit, PLL (Phase-locked loop) and threshold DACs (Digital to Analog Converters). This paper will describe the ASIC architecture and the experimental results of the first HKROC prototype received in January 2022.
The design and measurement results of two low power DLL prototypes for applications in particle physics readout systems are presented. The DLLs were fabricated in two different 130 nm CMOS ...technologies, called process A and process B, giving the opportunity to compare these two CMOS processes. Both circuits generate 64 uniform clock phases and operate at similar frequency range, from 20 MHz up to 60 MHz (10 MHz - 90 MHz in process B). The period jitter of both DLLs is in the range 2.5 ps - 12.1 ps (RMS) and depends on the selected output phase. The complete DLL functionality was experimentally verified, confirming a very low and frequency scalable power consumption of around 0.7 mW at typical 40 MHz input. The DLL prototype, designed in process A, occupies 680 mum x 210 mum, while the same circuit designed in process B occupies 430 mum x 190 mum.
PDF
