Most simulations of communications systems are done using a high-level language such as Matlab or C. As the complexity of these simulations grows and higher performance is expected, the runtime of ...the simulations becomes unacceptable. A promising solution to this problem is to move frequently executed (bottleneck) sections of the simulation into dedicated hardware that is implemented on field-programmable gate arrays (FPGAs). An FPGA, coupled with a very high-speed interface to the PC, is an ideal platform for such an accelerator. The system described in this paper is based on a PCI board with multiple Xilinx FPGAs. A typical wireless communications channel can be described as a finite impulse response (FIR) filter with time-varying coefficients. In this paper a FIR filter is implemented using dedicated hardware mapped onto a Xilinx FPGA board. The filter has additional hardware that interpolates between adjacent coefficients for more continuous and realistic results. The same filter is created in optimized Matlab for software simulation. Another common algorithm implemented in modern communication systems is a fast Fourier transform (FFT). This paper compares the software simulation and co-simulation approaches for both the FIR and the FFT blocks. Dramatic improvements in overall simulation throughput are demonstrated by using the hardware accelerator, as opposed to a pure software simulation
This paper presents a hardware-centric implementation of the symbol level processing for the WCDMA downlink. The presented architecture allows much lower power consumption than a traditional ...DSP-centric approach. The symbol level decoding blocks include: power control bit extraction, control/data separation, data scaling and quantization, 2/sup nd/ deinterleaving. The system-level architecture, including the interfacing of the hardware blocks to the /spl mu/P and the memory sizing, is described and justified. The system includes intelligent bus arbitration to allow single-port memory to be used for all data storage.
A silicon implementation of a dual antenna mobile station modem for 3G WCDMA is presented. Diversity processing is used to support data rates up to 2 Mb/s while reducing power consumption. An average ...SNR improvement of 7 dB has been observed yielding up to a 4x increase in capacity with no change to the exisiting network infrastructure.
The processing requirements for high speed data communication systems (symbol rates in excess of 5 MHz) are beyond the capabilities of programmable devices such as DSP chips and FPGAs. Designers of ...such systems have traditionally incurred the high none recurring engineering (NRE) costs and long development times associated with custom ASIC implementations. In this paper we highlight an emerging trend in the development of parametrizable, high speed datapaths for application in data communications. Such circuits can deliver the high throughputs associated with traditional ASIC implementations while at the same time provide the user with the ability to vary key system parameters, or even redefine the circuit functionality among a finite number of alternatives. They have the potential to significantly reduce the cost of implementing high-speed data communication systems by reducing the NRE costs. Moreover, the ability to use the same piece of hardware in a large number of different systems provides further price reductions due to economies of scale. In order to bring out key concepts associated with the design of such systems, the paper provides an in-depth description of three sample circuits. They are: (a) A versatile rake-receiver architecture for use in DSSS-CDMA based systems; (b) A highly reconfigurable baseband processing engine for application in a host of systems based on single carrier modulation; and (c) A highly versatile beamforming IC.
A new flexible architecture is proposed for word-serial filtering and variable rate decimation/interpolation. The architecture is targeted for low power applications requiring medium to low data rate ...and is ideally suited for implementation on either an ASIC or an FPGA. It combines the small size and low power of an ASIC with the programmability and flexibility of a DSP. An efficient memory addressing scheme eliminates the need for power hungry shift registers and allows full reconfiguration via a single ROM. The decimation ratio, filter length and filter coefficients can all be changed in real-time. The architecture takes advantage of coefficient symmetries in linear phase filters and in polyphase components.
Vibratory gyroscopes exploit a coriolis force coupling between two degrees of freedom internal to the sensor for detection of the sensor's angular rotation rate. Vibratory gyroscopes provide ...ubiquitous opportunities for local feedback compensation to achieve harmonic excitation of selected modes, disturbance rejection, and tuning of the sensor's dynamics. This paper describes the design and preliminary testing of an application specific integrated circuit (ASIC) that performs some of these control tasks in addition to the signal demodulation required for the detection of the rate-induced response.
A flexible and reconfigurable signal processing ASIC architecture has been developed, simulated and synthesized. The proposed architecture can be used to realize any one of several functional blocks ...needed for the physical layer implementation of high speed data communication systems operating at symbol rates over 60 Msamples/sec. In fact, multiple instances of a chip based on this architecture each operating in a different mode can be used to realize the entire physical layer of high speed data communication systems. The architecture features the following modes (functions); real and complex FIR/IIR filtering, least mean square (LMS) based adaptive filtering, Discrete Fourier Transforms (DFT), and direct digital frequency synthesis (DDFS) at up to 60 Msamples/sec. All of the modes are mapped onto a common, regular datapath with minimal configuration logic and routing. Multiple chips operating in the same mode can be cascaded to allow for larger blocks.
This paper introduces a new approach to direct digital frequency synthesis (DDFS) based on the Coordinate Rotation (CORDIC) algorithm. The modifications to the standard CORDIC algorithm introduced in ...this paper allow fine frequency resolution, and exhibit significant potential for low power applications. The new architecture does not need a large ROM and can be implemented on a general purpose processor, or on a flexible ASIC architecture.
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