The insertable B-Layer upgrade of the ATLAS pixel detector forsees the installation of a fourth pixel layer close to the beam pipe inside the current ATLAS pixel detector. A new readout chip (FE-I4) ...has been developed to match the increased requirements in terms of radiation hardness and hit occupancy. A new USB-based test system for ATLAS hybrid pixel detectors (USBpix) will serve as test bench for this new readout chip generation. The performance of USBpix is compared to the performance of the TPLL/TPCC system, used for testing the ATLAS pixel detector readout chips FE-I3 and modules. The main differences between the FE-I3 and the FE-I4 are summarized from the point of view of the test systems and the implementation of the main blocks for chip configuration, data storage and histogramming in the USBpix FPGA firmware for both chip generations is discussed. Results of the first measurements which were done using the FE-I4 emulator developed for debugging purposes are discussed.
Abstract
The High Granularity Timing Detector (HGTD) will be
installed in the ATLAS detector to mitigate pile-up effects during
the High Luminosity (HL) upgrade of the Large Hadron Collider (LHC)
at ...CERN. The design of the HGTD is based on the use of Low Gain
Avalanche Detectors (LGADs), with an active thickness of
50 μm, that allow to measure with high-precision the time of
arrival of particles. The HGTD will improve the particle-vertex
assignment by measuring the track time with a resolution ranging
from approximately 30 ps at the beginning of the HL-LHC operations
to 50 ps at the end. Performances of several unirradiated, as well
as neutron- and proton-irradiated, LGAD sensors from different
vendors have been measured in beam test campaigns during the years
2018 and 2019 at CERN SPS and DESY. This paper presents the results
obtained with data recorded by an oscilloscope synchronized with a
beam telescope which provides particle position information within a
resolution of a few μm. Collected charge, time resolution and
hit efficiency are presented. In addition to these properties, the
charge uniformity is also studied as a function of the position of
the incident particle inside the sensor pad.
The upgrade to the High Luminosity Large Hadron Collider will increase the instantaneous luminosity by more than a factor of 5, thus creating significant challenges to the tracking systems of all ...experiments. Recent advancement of active pixel detectors designed in CMOS processes provide attractive alternatives to the well-established hybrid design using passive sensors since they allow for smaller pixel sizes and cost effective production. This article presents studies of a high-voltage CMOS active pixel sensor designed for the ATLAS tracker upgrade. The sensor is glued to the read-out chip of the Insertable B-Layer, forming a capacitively coupled pixel detector. The pixel pitch of the device under test is 33×125μm2, while the pixels of the read-out chip have a pitch of 50×250μm2. Three pixels of the CMOS device are connected to one read-out pixel, the information of which of these subpixels is hit is encoded in the amplitude of the output signal (subpixel encoding). Test beam measurements are presented that demonstrate the usability of this subpixel encoding scheme.
High-voltage pixel sensors for ATLAS upgrade Perić, I.; Kreidl, C.; Fischer, P. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
11/2014, Letnik:
765
Journal Article
Recenzirano
Odprti dostop
The high-voltage (HV-) CMOS pixel sensors offer several good properties: a fast charge collection by drift, the possibility to implement relatively complex CMOS in-pixel electronics and the ...compatibility with commercial processes. The sensor element is a deep n-well diode in a p-type substrate. The n-well contains CMOS pixel electronics. The main charge collection mechanism is drift in a shallow, high field region, which leads to a fast charge collection and a high radiation tolerance. We are currently evaluating the use of the high-voltage detectors implemented in 180nm HV-CMOS technology for the high-luminosity ATLAS upgrade. Our approach is replacing the existing pixel and strip sensors with the CMOS sensors while keeping the presently used readout ASICs. By intelligence we mean the ability of the sensor to recognize a particle hit and generate the address information. In this way we could benefit from the advantages of the HV sensor technology such as lower cost, lower mass, lower operating voltage, smaller pitch, smaller clusters at high incidence angles. Additionally we expect to achieve a radiation hardness necessary for ATLAS upgrade. In order to test the concept, we have designed two HV-CMOS prototypes that can be readout in two ways: using pixel and strip readout chips. In the case of the pixel readout, the connection between HV-CMOS sensor and the readout ASIC can be established capacitively.
Luminosity upgrades are discussed for the LHC (HL-LHC) which would make updates to the detectors necessary, requiring in particular new, even more radiation-hard and granular, sensors for the inner ...detector region. A proposal for the next generation of inner detectors is based on HV-CMOS: a new family of silicon sensors based on commercial high-voltage CMOS technology, which enables the fabrication of part of the pixel electronics inside the silicon substrate itself. The main advantages of this technology with respect to the standard silicon sensor technology are: low material budget, fast charge collection time, high radiation tolerance, low cost and operation at room temperature. A traditional readout chip is still needed to receive and organize the data from the active sensor and to handle high-level functionality such as trigger management. HV-CMOS has been designed to be compatible with both pixel and strip readout. In this paper an overview of HV2FEI4, a HV-CMOS prototype in 180 nm AMS technology, will be given. Preliminary results after neutron and X-ray irradiation are shown.
In order to extend its discovery potential, the Large Hadron Collider (LHC) will have a major upgrade (Phase II Upgrade) scheduled for 2022. The LHC after the upgrade, called High-Luminosity LHC ...(HL-LHC), will operate at a nominal leveled instantaneous luminosity of 5x 10 super(34) cm super(?2) s super(?1), more than twice the expected Phase I . The new Inner Tracker needs to cope with this extremely high luminosity. Therefore it requires higher granularity, reduced material budget and increased radiation hardness of all components. A new pixel detector based on High Voltage CMOS (HVCMOS) technology targeting the upgraded ATLAS pixel detector is under study. The main advantages of the HVCMOS technology are its potential for low material budget, use of possible cheaper interconnection technologies, reduced pixel size and lower cost with respect to traditional hybrid pixel detector. Several first prototypes were produced and characterized within ATLAS upgrade R&D effort, to explore the performance and radiation hardness of this technology. In this paper, an overview of the HVCMOS sensor concepts is given. Laboratory tests and irradiation tests of two technologies, HVCMOS AMS and HVCMOS GF, are also given.
Large detectors in high-energy physics experiments are mostly built from many identical individual building blocks, called modules, which possess individual parts of the services. The modules are ...usually also powered by parallel power lines such that they can be individually operated. The main disadvantage of such a parallel powering scheme is the vast amount of necessary power cables which constitutes also a large amount of material in the path of the particles to be detected. For the LHC experiments already now this is a major problem for the optimal performance of the detectors and it has become evident, that for an upgrade programme alternative powering schemes must be investigated. We prove and demonstrate here for the example of the large scale pixel detector of ATLAS that Serial Powering of pixel modules is a viable alternative. A powering scheme using dedicated voltage regulators and modified flex hybrid circuits has been devised and implemented for ATLAS pixel modules. The modules have been intensively tested in the lab and in test beams and have been compared to those powered in parallel with respect to noise and threshold stability performance. Finally, the equivalent of a pixel ladder consisting of six serially powered pixel modules with about 0.3
Mpixels has been built and the performance with respect to operation failures has been studied.
In 2014 the Insertable B-Layer (IBL) will extend the existing Pixel Detector of the ATLAS experiment at CERN by over 12 million additional pixels. For calibration and monitoring purposes, occupancy ...and time-over-threshold data are being histogrammed in the read-out hardware. Further processing of the histograms happens on commodity hardware, which not only requires the fast transfer of histogram data from the read-out hardware to the computing farm via Ethernet, but also the integration of the software and hardware into the already existing data-acquisition and calibration framework (TDAQ and PixelDAQ) of the ATLAS experiment and the current Pixel Detector. We implement the software running on the compute cluster with an emphasis on modularity, allowing for flexible adjustment of the infrastructure and a good scalability with respect to the number of network interfaces, available CPU cores, and deployed machines. By using a modular design we are able to not only employ CPU-based fitting algorithms, but also have the possibility to take advantage of the performance offered by a GPU-based approach to fitting.
The ATLAS experiment at LHC planned to upgrade the existing Pixel Detector with the insertion of an innermost silicon layer, called Insertable B-layer (IBL). A new front-end ASIC has been foreseen ...(named FE-I4) and it will be read out with improved off-detector electronics. In particular, the new Read-Out Driver card (ROD) is a VME-based board designed to process a fourfold data throughput. Moreover, the ROD hosts the electronics devoted to control operations whose main tasks are providing setup busses to access configuration registers on several FPGAs, receiving configuration data from external PCs, managing triggers and running calibration procedures. In parallel with a backward-compatible solution with a Digital Signal Processor (DSP), a new ROD control circuitry with a PowerPC embedded into an FPGA has been implemented. In this paper the status of the PowerPC-based control system will be outlined with major focus on firmware and software development strategies.
EUDAQ is a generic data acquisition software developed for use in conjunction with common beam telescopes at charged particle beam lines. Providing high-precision reference tracks for performance ...studies of new sensors, beam telescopes are essential for the research and development towards future detectors for high-energy physics. As beam time is a highly limited resource, EUDAQ has been designed with reliability and ease-of-use in mind. It enables flexible integration of different independent devices under test via their specific data acquisition systems into a top-level framework. EUDAQ controls all components globally, handles the data flow centrally and synchronises and records the data streams. Over the past decade, EUDAQ has been deployed as part of a wide range of successful test beam campaigns and detector development applications.
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