Due to superior material properties of SiC for high-voltage devices, SiC Schottky diodes are used in energy-conversion systems such as solar-cell inverters, battery chargers, and power modules for ...electric cars and unmanned aerial vehicles. The reliable operation of these systems requires the chip temperature of SiC Schottky diodes to be maintained within the limit set by the device package. This is especially crucial during surge-current events that dissipate heat within the device. As a thermal-management method, manufactures of commercial SiC Schottky diodes have introduced wafer thinning practices to reduce the thickness of the SiC chip and, consequently, to reduce its thermal resistance. However, this also leads to a reduction in the thermal capacitance. In this paper, we present experimental data and theoretical analysis to demonstrate that the reduced thermal capacitance has a much larger adverse effect in comparison to the beneficial reduction of the thermal resistance. An implication of the presented results is that, contrary to the adopted wafer thinning practices, SiC Schottky diodes fabricated without wafer thinning have superior surge-current capability.
Characterization of near-interface traps (NITs) in commercial SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) is essential because they adversely impact both performance and ...reliability by reducing the channel carrier mobility and causing threshold-voltage drift. In this work, we have applied a newly developed integrated-charge technique to measure the density of NITs that are active in the above-threshold region of commercial SiC MOSFETs. The results demonstrate that NITs trap about 10% of the channel electrons for longer than 500 ns.
The performance and reliability of the state-of-the-art power 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) are affected by electrically active defects at and near the interface ...between SiC and the gate dielectric. Specifically, these defects impact the channel-carrier mobility and threshold voltage of SiC MOSFETs, depending on their physical location and energy levels. To characterize these defects, techniques have evolved from those used for Si devices to techniques exclusively designed for the SiC MOS structure and SiC MOSFETs. This paper reviews the electrically active defects at and near the interface between SiC and the gate dielectric in SiC power MOSFETs and MOS capacitors. First, the defects are classified according to their physical locations and energy positions into (1) interface traps, (2) near interface traps with energy levels aligned to the energy gap, and (3) near-interface traps with energy levels aligned to the conduction band of SiC. Then, representative published results are shown and discussed for each class of defect.
Measurements of the near-interface oxide traps (NIOTs) aligned to the conduction band of silicon-carbide (SiC) are of particular importance as these active defects are responsible for degradation of ...the channel-carrier mobility in 4H-SiC MOSFETs. In this brief, a new method for measurement of the active NIOTs with energy levels aligned to the conduction band is proposed. The method utilizes transient-current measurements on 4H-SiC MOS capacitors biased in accumulation. Nitrided oxide and dry oxide are used to illustrate the applicability of the proposed measurement method.
The state-of-the-art 4H-SiC MOSFETs still suffer from performance (low channel-carrier mobility and high threshold voltage) and reliability (threshold voltage instability) issues. These issues have ...been attributed to a large density of electrically active defects that exist in the SiO2–SiC interfacial region. This paper reviews the earlier and the latest results about the responsible defects for the performance and reliability issues of SiC MOS devices, in the context of the evolution of physical understanding of these defects. The aim of this critical review is to clarify possible confusions due to inconsistencies between the earlier and the latest results. Specific clarifications relate to the physical position of the active defects (whether they are located at or near the SiO2–SiC interface) and the energy position of their energy levels (above or below the bottom of conduction band).
We investigate the impact of power MOSFET channel width on the power efficiency of a switch-mode power supply. With this analysis, we derive a circuit-specific criterion that minimizes the power ...dissipated by a power MOSFET, which is based on the ratio between on resistance and output capacitance of the MOSFET and is independent of its technological parameters. The effect of channel width on the power dissipation is illustrated by simulation-based analysis, which also provide an example of a published non-optimum selection of a power MOSFET and demonstrate the advantage of the newly proposed method for MOSFET selection.
Very fast interface traps have recently been suggested to be the main cause behind the rather poor inversion channel mobility in nitrided SiC metal-oxide-semiconductor-field-effect-transistors ...(MOSFETs). Using capacitance voltage analysis and conductance spectroscopy on metal oxide semiconductor capacitors, at cryogenic temperatures, we find that these fast traps are absent in oxides made by sodium enhanced oxidation, and high inversion channel-carrier mobility in MOSFETs made by sodium enhanced oxidation is observed.
Oxide traps existing in 4H-SiC MOS capacitors with fast response times that are active in the strong accumulation and depletion regions were characterized by an integrated-charge method. The method ...is based on the measurement of charging and discharging voltages across MOS capacitors in response to high-frequency voltage pulses. This method can identify traps with response times in the order of hundreds of nanoseconds. The results reveal an increasing density of near-interface traps with energy levels above the bottom of the conduction band, which are the active defects reducing the channel-carrier mobility in 4H-SiC MOSFETs.
Very fast interface traps have recently been suggested to be the main cause behind poor channel-carrier mobility in SiC metal–oxide–semiconductor field effect transistors. It has been hypothesized ...that the NI traps are defects located inside the SiO2 dielectric with energy levels close to the SiC conduction band edge and the observed conductance spectroscopy signal is a result of electron tunneling to and from these defects. Using aluminum nitride and aluminum oxide as gate dielectrics instead of SiO2, we detect NI traps at these SiC/dielectric interfaces as well. A detailed investigation of the NI trap density and behavior as a function of temperature is presented and discussed. Advanced scanning transmission electron microscopy in combination with electron energy loss spectroscopy reveals no SiO2 at the interfaces. This strongly suggests that the NI traps are related to the surface region of the SiC rather than being a property of the gate dielectric.
This brief presents direct electrical measurement of active defects in the strong-accumulation region of N-type 4H-SiC MOS capacitors, which corresponds to the strong-inversion region of N-channel ...MOSFETs. The results demonstrate the existence of an active defect in the gate oxide, located very close to the SiC surface, with localized energy levels between 0.13 eV and 0.23 eV above the bottom of the conduction band. The observed spatial and energy localizations indicates that this is a well-defined defect.
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