During the shutdown of the CERN Large Hadron Collider in 2013-2014, an additional pixel layer was installed between the existing Pixel detector of the ATLAS experiment and a new, smaller radius beam ...pipe. The motivation for this new pixel layer, the Insertable B-Layer (IBL), was to maintain or improve the robustness and performance of the ATLAS tracking system, given the higher instantaneous and integrated luminosities realised following the shutdown. Because of the extreme radiation and collision rate environment, several new radiation-tolerant sensor and electronic technologies were utilised for this layer. This paper reports on the IBL construction and integration prior to its operation in the ATLAS detector.
A monolithic pixelated silicon detector designed for high time resolution has been produced in the SG13G2 130 nm SiGe BiCMOS technology of IHP. This proof-of-concept chip contains hexagonal pixels of ...65 μm and 130 μm side. The SiGe front-end electronics implemented provides an equivalent noise charge of 90 and 160 e− for a pixel capacitance of 70 and 220 fF, respectively, and a total time walk of less than 1 ns. Lab measurements with a 90Sr source show a time resolution of the order of 50 ps. This result is competitive with silicon technologies that integrate an avalanche gain mechanism.
The Picosecond Avalanche Detector is a multi-junction silicon pixel detector devised to enable charged-particle tracking with high spatial resolution and picosecond time-stamping capability. A ...proof-of-concept prototype of the PicoAD sensor has been produced by IHP microelectronics. Measurements with a 55Fe X-ray radioactive source show that the prototype is functional with an avalanche gain up to a maximum electron gain of 23.
High voltage CMOS pixel sensors will be or are proposed to be used in several particle physics experiments for particle tracking like Mu3e experiment. ATLASPIX3 is the first full reticle size ...monolithic HVCMOS sensor for construction of multi-chip modules. The specifications for the use case have been taken from ATLAS pixel upgrade in fifth layer where it was a candidate for. The size of the chip is 2.0×2.1 cm2 with periphery at one side which makes the chip 3-side buttable. ATLASPIX3 has been implemented in a standard 180 nm HVCMOS process. Each pixel has an area of 150×50μm2 and contains a large charge collecting electrode implemented as deep n-well. The depleted volume around the n-well is enlarged by a high voltage bias and the usage of higher resistivity substrate. The readout electronics supports both triggered and triggerless readout with zero-suppression. ATLASPIX3 could be used for the construction of CMOS modules for particle tracking in experiments where high time resolution, high radiation tolerance, low power and low material budget are required. In the design phase, special attention has been paid to decreasing timing differences between pixels and the rate capability of the readout.
Abstract
The FASER experiment is a new small and inexpensive experiment that is placed 480 meters downstream of the ATLAS experiment at the CERN LHC. FASER is designed to capture decays of new ...long-lived particles, produced outside of the ATLAS detector acceptance. These rare particles can decay in the FASER detector together with about 500–1000 Hz of other particles originating from the ATLAS interaction point. A very high efficiency trigger and data acquisition system is required to ensure that the physics events of interest will be recorded. This paper describes the trigger and data acquisition system of the FASER experiment and presents performance results of the system acquired during initial commissioning.
Abstract
A 33.6 ps LSB Time-to-Digital converter was designed in 130 nm BiCMOS technology. The core of the converter is a differential
9-stage ring oscillator, based on a multi-path architecture. A ...novel
version of this design is proposed, along with an analytical model
of linearity. The model allowed us to understand the source of the
performance superiority (in terms of linearity) of our design and to
predict further improvements. The oscillator is integrated in a
event-by-event self-calibration system that allows avoiding any
PLL-based synchronization. For this reason and for the compactness
and simplicity of the architecture, the proposed TDC is suitable for
applications in which a large number of converters and a massive
parallelization are required such as High-Energy Physics and medical
imaging detector systems. A test chip for the TDC has been
fabricated and tested. The TDC shows a DNL≤1.3 LSB, an
INL≤2 LSB and a single-shot precision of 19.5 ps (0.58
LSB). The chip dissipates a power of 5.4 mW overall.
Abstract
This paper presents a small-area monolithic pixel detector
ASIC designed in 130 nm SiGe BiCMOS technology for the upgrade of
the pre-shower detector of the FASER experiment at CERN. The ...purpose
of this prototype is to study the integration of fast front-end
electronics inside the sensitive area of the pixels and to identify
the configuration that could satisfy at best the specifications of
the experiment. Self-induced noise, instabilities and cross-talk
were minimised to cope with the several challenges associated to the
integration of pre-amplifiers and discriminators inside the pixels.
The methodology used in the characterisation and the design choices
will also be described. Two of the variants studied here will be
implemented in the pre-production ASIC of the FASER experiment
pre-shower for further tests.
Abstract
A monolithic silicon pixel detector prototype has been
produced in the SiGe BiCMOS SG13G2 130 nm node technology by
IHP. The ASIC contains a matrix of hexagonal pixels with pitch of
...approximately 100 μm. Three analog pixels were calibrated in
laboratory with radioactive sources and tested in a 180 GeV/c pion
beamline at the CERN SPS. A detection efficiency of
(99.9
-0.2
+0.1
)% was measured together with a time
resolution of (36.4 ± 0.8) ps at the highest preamplifier bias
current working point of 150 μA and at a sensor bias voltage
of 160 V. The ASIC was also characterized at lower bias voltage and
preamplifier current.
Abstract
This contribution presents simulation results, implementation, and first tests of a
monolithic detector developed at KIT. It consists of a sensor diode tightly integrated with an
analogue ...front-end based on SiGe (Silicon-Germanium) SG13G2 130 nm BiCMOS technology produced at
the Leibniz Institute for High Performance Microelectronics (IHP). The pixel size is
100 μm × 100 μm, and the nwell charge collection node dimensions were reduced
to 10 μm × 10 μm. We investigate the influence of this approach on sensor
performance, spatial resolution via charge sharing and timing behaviour.
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