The SLIM5 low mass silicon tracker demonstrator Bettarini, S.; Ratti, L.; Rizzo, G. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
11/2010, Letnik:
623, Številka:
3
Journal Article
Recenzirano
A low material budget silicon demonstrator has been tested by the SLIM5 collaboration with 12
GeV/
c protons at the PS-T9 beam line at CERN. Two devices were placed inside a reference telescope and ...their characteristics were measured. The first was a 4k-Pixel Matrix of Deep N Well MAPS, developed in a 130
nm CMOS technology, providing digital sparsified readout. The other one was a high resistivity double-sided silicon detector, with short strips at a
45
∘
angle to the detector's edge, read out by the FSSR2 chip. In this paper we describe the main features of both sensors. The primary goal of the test was to measure the efficiency and the resolution of the DUTs under different conditions of threshold setting and incident angle of the impinging particles. The data-driven approach of the readout chips has been fully exploited by the DAQ system to take data with a track-based level-1 trigger provided by a pattern matching algorithm with very low latency.
The results obtained by the Slim5 collaboration on a low material budget tracking silicon demonstrator put on a 12
GeV/
c
proton test beam at CERN are reported. Inside a reference telescope, two ...different and innovative detectors were placed for careful tests. The first was a 4k-Pixel Matrix of Deep N Well MAPS, developed in a 130
nm CMOS Technology, square pixels
50
μ
m
wide, thinned down to
100
μ
m
and equipped with a digital sparsified readout running up to 50
MHz. The other was a high resistivity double sided silicon detector,
200
μ
m
thick, with short strips with
50
μ
m
pitch at
45
∘
angle to the detector's edge. The detectors were equipped with dedicated fast readout architectures performing on-chip data sparsification and providing the timing information for the hits. The criteria followed in the design of the pixel sensor and of the pixel readout architecture will be reviewed. Preliminary measurements of the pixel charge collection, track detection efficiencies and resolutions of pixel and strip sensors are discussed.
The data driven architecture of the readout chips has been fully exploited in the test beam by a data acquisition system able to collect on electronic board up to 2.5 Million events per second before triggering. By using a dedicated Associative Memory board, we were able to perform a level 1 trigger system, with minimal latency, identifying cleanly tracks traversing the detectors. System architecture and main performances are shown.
The S uperB silicon vertex tracker Forti, F.; Avanzini, C.; Batignani, G. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
2011, Letnik:
636, Številka:
1
Journal Article
Recenzirano
The S
uperB asymmetric e
+e
− collider, to be built near the INFN National Frascati Laboratory in Italy, has been designed to deliver a luminosity greater than 10
36
cm
−2
s
−1 with moderate beam ...currents, allowing precision measurements in the flavour sector sensitive to New Physics. The conceptual design of the Silicon Vertex Tracker for the S
uperB Detector is presented, based on double-sided silicon strip detectors for the outer layers, with the addition of an innermost Layer 0 close to the interaction point, with low material budget and capable of sustaining a background rate of several MHz/cm
2.
The high luminosity asymmetric e + e - collider SuperB, recently approved by the Italian Government, is designed to deliver a luminosity greater than 10 36 cm -2 s -1 with moderate beam currents and ...a reduced center of mass boost with respect to earlier B-Factories. An improved vertex resolution is required for precise time-dependent measurements and the SuperB Silicon Vertex Tracker will be equipped with an innermost layer of small radius (about 1.5 cm), resolution of 10 μm in both coordinates, low material budget (<;1% X 0 ), and able to withstand a hit background rate of several tens of MHz/cm 2 . The ambitious goal of designing a thin pixel device matching these stringent requirements is being pursued with specific R&D programs on different technologies: CMOS MAPS, pixel sensors in vertical integration technology and hybrid pixels with small pitch and reduced material budget. The latest results on the characterization of the various pixel devices realized for the SuperB Layer0 will be presented.
We report on further developments of our recently proposed design approach for a full in-pixel signal processing chain of deep n-well (DNW) MAPS sensors, by exploiting the triple well option of a ...CMOS 0.13 μm process. The optimization of the collecting electrode geometry and the re-design of the analog circuit to decrease power consumption have been implemented in two versions of the APSEL chip series, namely "APSEL3T1" and "APSEL3T2". The results of the characterization of 3x3 pixel matrices with full analog output with photons from 55 Fe and electrons from 90 Sr are described. Pixel equivalent noise charge (ENC) of 46 e- and 36 e- have been measured for the two versions of the front-end implemented toghether with signal-to-noise ratios between 20 and 30 for Minimum Ionizing Particles. In order to fully exploit the readout capabilities of our MAPS, a dedicated fast readout architecture performing on-chip data sparsification and providing the timing information for the hits has been implemented in the prototype chip "APSEL4D", having 4096 pixels. The criteria followed in the design of the readout architecture are reviewed. The implemented readout architecture is data-driven and scalable to chips larger than the current one, which has 32 rows and 128 columns. Tests concerning the functional characterization of the chip and response to radioactive sources have shown encouraging preliminary results. A successful beam test took place in September 2008. Preliminary measurements of the APSEL4D charge collection efficiency and resolution confirmed the DNW device is working well. Moreover the data driven approach of the readout chips has been successfully used to demonstrate the possibility to build a Level 1 trigger system based on Associative Memories.
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