The future upgrades of the LHC experiments will increase the beam luminosity leading to a corresponding growth of the amounts of data to be treated by the data acquisition systems. To address these ...needs, the GBT (Giga-Bit Transceiver optical link 1,2) architecture was developed to provide the simultaneous transfer of readout data, timing and trigger signals as well as slow control and monitoring data. The GBT-SCA ASIC, part of the GBT chip-set, has the purpose to distribute control and monitoring signals to the on-detector front-end electronics and perform monitoring operations of detector environmental parameters. In order to meet the requirements of different front-end ASICs used in the experiments, it provides various user-configurable interfaces capable to perform simultaneous operations. It is designed employing radiation tolerant design techniques to ensure robustness against SEUs and TID radiation effects and is implemented in a commercial 130 nm CMOS technology. This work presents the GBT-SCA architecture, the ASIC interfaces, the data transfer protocol, and its integration with the GBT optical link.
Abstract
The increase in complexity and size of modern ASIC designs in the HEP community and the use of advanced semiconductor fabrication processes raises the need for a shift toward a more abstract ...design methodology, that takes advantage of modularity and programmability to achieve a faster turnaround time both for design and verification. This contribution will present two complementary approaches, one using a RISC-V based System-on-Chip (SoC) and the other based on Application-Specific Instruction set Processors (ASIP). The SoC uses the PicoRV32 open-source RISC-V core and a rad-hard version of the AMBA APB bus to connect peripherals and is primarily geared towards control and monitoring applications. This solution is a demonstrator of what can become a more complete fully radiation-tolerant SoC platform with a standardized interconnect and an IP block library, to serve as the starting point for future ASIC designs. The ASIP based approach targets more the design of data path elements and the use in data processing applications. The presented approach makes use of a commercial ASIP Designer EDA tool to demonstrate an integrated workflow to define, benchmark and optimize an ASIP for a specific use case, starting from a general-purpose processor.
Abstract
The MPA and SSA development is approaching the production phase with an approximate volume of more than 200k ASICs, corresponding to 1200 wafers. The limited manufacturing yield requires ...testing strategies able to identify defective units and guarantee the correct functionality of the tracker modules. This contribution presents innovative methods to replace the currently used functional tests for the digital part of the ASICs, showing limited testing accuracy and long testing time. The proposed solution exploits the concept of structural test and new testing algorithms such as Automatic Test Pattern Generation (ATPG) for general digital logic and March for memory elements. Design for Testability (DFT) hardware is integrated on chip to test SRAM memories, peripheral logic and MPA pixel array, providing internal control and observation points for the implementation of the those algorithms. Particular attention is given to power increase, timing and placement impact as well as radiation tolerance of the introduced circuitry, which must be fully transparent during the normal operation of the chip. A faster and more accurate testing approach is presented, from design methodology to implementation choices and silicon results, for a reliable and cost effective testing procedure.
Abstract
For the Phase II upgrade at HL-LHC, CMS needs a new Outer Tracker detector able to cope with reduced material budget, increased radiation tolerance and higher pile-up conditions with respect ...to LHC. The main feature of the Outer Tracker will be its inclusion at the first level of the CMS trigger system with data readout at 40 MHz. Two types of modules, Pixel-Strip and Strip-Strip will equip the Outer Tracker. Each module consists of a superposition of two silicon layers, able to detect charged particles, and an innovative readout electronics, allowing a significant data rate reduction. The Concentrator Integrated Circuit (CIC) is a 65 nm CMOS radiation tolerant front-end ASIC for both modules. It is considered a fundamental element of the future detector front-end chain due to its role in aggregating and compressing data from 8 front-end ASICs on each module. It reduces the data throughput by an order of magnitude. Two first version of the CIC were previously developed and tested. This paper will present the pre-production version, called CIC2.1, together with the functional and wafer test results.
Abstract
This contribution presents the results of the performance characterization and radiation tolerance evaluation of the SSA2 ASIC, the short-strip readout ASIC for the CMS Outer-Tracker ...PS-module. The ASIC performance is characterised by different temperatures and operating conditions, at the die level as well as at the wafer level. The radiation evaluation comprises Total-Ionising-Dose (TID) tests and Single-Event-Effects (SEEs). Wafer-level testing provided a large dataset to evaluate the production yield. The presented test results are in agreement with the design simulations and are well within the application requirements for operation in the CMS outer-tracker at the HL-LHC.
Abstract
The Concentrator Integrated Circuit (CIC) ASIC is a front-end chip for both Pixel-Strip (PS) and Strip-Strip (2S) modules of the future Phase-II CMS Outer Tracker upgrade at the ...High-Luminosity LHC (HL-LHC). This data aggregator, designed in 65 nm CMOS technology, will be a key element of the tracker front-end chain. A first prototype, CIC1, was tested successfully in early 2019 and was followed by the development of a final radiation tolerant version of the chip: the CIC2. CIC2 design, implementation, and complete test results, are presented.
Abstract
A Scalable Low Voltage Signaling (SLVS) transmitter and receiver have been developed as IP blocks in a 28 nm standard CMOS technology for the future upgrades for the high luminosity LHC. At ...the target data rate of 1.28 Gbps, the transmitter consumes 6 mW and the receiver consumes 2 mW. The transmitter’s output is powered with 1.2 V to provide compatibility with previous designs, while the core logic can be powered with 0.8 V to reduce power consumption. This work summarizes the design approach at the schematic and layout level. Practical aspects of the novel technology for the design of ASICs in High Energy Physics will be discussed along with characterization results. Other IP blocks are being designed (ADC, DAC, PLL) and they will be presented.
Abstract
A test chip with 368 ring-oscillators and 4 different SRAMs has been designed to study the effect of total ionizing dose on a commercial 28 nm CMOS technology. The chip has been exposed to 1 ...Grad(SiO
2
), followed by a week of annealing at
T
= 100 °C. The results will be compared to those obtained on single (i.e., isolated) devices in the same 28 nm process and on a similar chip in 65 nm CMOS technology. This test confirms the robustness of the 28 nm technology to ionizing radiation, enabling the development of ASICs capable of surviving in environments with hundreds of Mrad.
The radiation characteristics with respect to Total Ionizing Dose (TID) and Single-Event Upsets (SEUs) of a 65 nm CMOS technology have been investigated. Single transistor structures of a variety of ...dimensions and several basic circuits were designed and fabricated. The circuits include a 64-kbit shift-register, a 56-kbit SRAM and a ring-oscillator. The test chips were irradiated up to 200 Mrad with an X-ray beam and the corresponding transistor threshold shifts and leakage currents were measured. Heavy-ion beam irradiation was performed to assess the SEU sensitivity of the digital parts. Overall, our results give the confidence that the chosen 65 nm CMOS technology can be used in future High Energy Physics (HEP) experiments even without Hardness-By-Design (HBD) solutions, provided that constant monitoring of the TID response is carried out during the full manufacturing phase of the circuits.
We discuss design issues related to the extensive use of Enclosed Layout Transistors (ELT's) and guard rings in deep submicron CMOS technologies in order to improve radiation tolerance of ASIC's ...designed for the LHC experiments (the Large Hadron Collider at present under construction at CERN). We present novel aspects related to the use of ELT's: noise measured before and after irradiation up to 100 Mrad (SiO/sub 2/), a model to calculate the W/L ratio and matching properties of these devices. Some conclusions concerning the density and the speed of IC's conceived with this design approach are finally drawn.
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