High endurance ovonic threshold switch (OTS, here, TeAsGeSiSe-based) is integrated with phase change memory (PCM, here, doped Ge2Sb2Te5) to form a 3-D stackable pillar-type device. With the help of ...an etch buffer layer and a damage-free pillar reactive-ion etching process, we successfully demonstrate one-selector (OTS)/one-resistor (PCM) (1S1R OTS-PCM) pillar device without OTS/PCM composition modification. High temperature 400 °C annealing tests show this 1S1R OTS-PCM pillar device is back end of line compatible. We report the fundamental behavior of the OTS and the operation scheme of the 1S1R OTS-PCM device. The new Vth read scheme is proposed and excellent electrical performance is demonstrated. It provides the fast turn ON/ OFF speed which enables 10-ns fast RESET speed. Program endurance greater than 10 9 cycles is achieved, and read endurance is higher than 10 11 cycles.
Resistance of transition metal oxide (TMO) resistive random access memory (ReRAM) depends sharply on temperature, resulting in drastic memory window loss at high temperature. Thus, it is difficult to ...design the ReRAM that can serve a wide range of operating conditions. It is especially challenging to achieve multi-level-cell (MLC) ReRAM because of the large temperature dependency. This letter investigates both the temperature and read bias dependencies of WOx ReRAM, and found both can be well understood by a modified space-charge limited conduction model. Using this model, we have designed a novel read scheme that varies the read bias according to the device temperature and compensates for the temperature effect on cell resistance. Since TMO ReRAM devices depend on defect states, cell-to-cell and cycle-to-cycle variations are naturally large. An algorithm is designed to address the variability. A 1-Mb WOx ReRAM array is fabricated to both characterize the bias and temperature dependencies and verify the new read scheme. A large and constant memory window is preserved for MLC across a wide temperature range (-40 °C-125 °C), suitable for high-reliability applications.
A body-tied FinFET bandgap engineered (BE)-silicon-oxide-nitride-oxide-silicon (SONOS) nand Flash device is successfully demonstrated for the first time. BE-SONOS device with a BE oxide-nitride-oxide ...barrier is integrated in the FinFET structure with a 30-nm fin width. FinFET BE-SONOS can overcome the unsolvable tradeoff between retention and erase speed of the conventional SONOS. Compared with the current floating-gate Flash devices, FinFET BE-SONOS provides both retention and erase-speed performance, while eliminating the scaling limitations and is, thus, an important candidate for further scaling of nand Flash
A TiOx/TiOxNy resistive random access memory (ReRAM) with a sidewall bottom electrode (BE) is demonstrated for the first time. Several interesting characteristics that are very desirable for high ...reliability memory applications are observed: (1) a stable RESET and SET resistance switching window even without write verification, (2) good 250 °C data retention, (3) ReRAM switching instability after cycling is monitored and corrected, resulting in good reliability, and (4) using only complementary metal oxide semiconductor (CMOS) familiar materials and processes, thus very manufacture-friendly. The thickness and quality of TiOx and TiOxNy are well controlled by plasma oxidation, and a large resistance switching window (>10×), a low operation voltage, and good reliability are realized.
The erase characteristics and mechanism of metal- Al 2 O 3 -nitride-oxide-silicon (MANOS) devices are extensively studied. We use transient analysis to transform the erase curve (V FB - time) into a ...J-E curve (J = transient current, E = field in the tunnel oxide) in order to understand the underlying physics. The measured erase current of MANOS is three orders of magnitude higher than that can be theoretically provided by substrate hole current. In addition, the erase current is very sensitive to the Al 2 O 3 processing condition - also inconsistent with substrate hole injection model. Thus, we propose that MANOS erase occurs through an electron detrapping mechanism. We have further carried out a refill test and its results support the detrapping model. Our results suggest that the interfacial layer between Al 2 O 3 and nitride is a key process that dominates the erase mechanism of MANOS.
A complementary metal oxide semiconductor (CMOS)-compatible WO x based resistive memory has been developed. The WO x memory layer is made from rapid thermal oxidation of W plugs. The device performs ...excellent electrical properties. The switching speed is extremely fast (${\sim}2$ ns) and the programming voltage (${<}1.4$ V) is low. For single-level cell (SLC) operation, the device shows a large resistance window, and $10^{8}$-cycle endurance. For multi-level cell (MLC) operation, it demonstrates 2-bit/cell storage with the endurance up to 10000 times. The rapid thermal oxidation (RTO) WO x resistance random access memory (RRAM) is very promising for both high-density and embedded memory applications.
The behavior of WO X resistive random access memory (ReRAM) is a strong function of the top electrode material, which controls the conduction mechanism and the forming process. When using a top ...electrode with low work function, the current conduction is limited by space charges. On the other hand, the mechanism becomes thermionic emission for devices with a high work function top electrode. These (thermionic) devices are also found to have higher initial resistance, reduced forming current, and larger resistance window. Based on these insights and considering the compatibility to complementary metal--oxide--semiconductor (CMOS) process, we proposed to use Ni as the top electrode for high performance WO X ReRAM devices. The new Ni/WO X /W device can be switched at a low current density less than $8\times 10^{5}$ A/cm 2 , with RESET/SET resistance ratio greater than 100, and extremely good data retention of more than 300 years at 85 °C.
Incremental-step-pulse programming (ISPP) is a key enabler for achieving tight V T distribution for MLC NAND Flash. The ISPP characteristics for BE-SONOS NAND Flash are studied extensively in this ...work. Experimentally we find that the ISPP slope is very close to 1 for BE-SONOS capacitors for a wide range of EOT and O1 variations. A theoretical model is developed to prove that ISPP slope~1 is a universal property for any charge-trapping devices, assuming charges are fully captured. However, when the device is integrated in various STI geometries, the ISPP slope is often degraded. This is due to the STI edge effect. Non-uniform injection happens along the channel width and degrades the programming efficiency at higher V T levels. The degradation of trans-conductance (g m ) and subthreshold slope (S.S) during programming validates the STI edge effect. We find that through process modifications for the STI edge, the ISPP slope can be improved.
A novel trapping-nitride-storage nonvolatile memory cell by using a gated-diode structure is proposed. An ultrathin nitride layer is introduced between the n-type and p-type regions of the diode. ...This layer acts as a dopant diffusion barrier that well defines the junction location. Meanwhile, it is thin enough that charge carriers can flow through it via direct tunneling at low field as being sensed. Good program/erase characteristics and acceptable reliability are presented. Finally, using a low-bandgap material to enhance the sensing current is suggested along with the preferred device structure.
Operation impact on endurance performance in GST-based phase change memory is investigated from small arrays to large test chips. SET operation induced electromigration and phase segregation are ...observed. For the first time, the RESET melting healing effect is proposed to partially repair the SET induced damage and further extend the endurance. This concept can be easily implemented by accordingly designing the control circuits.
