The SLIM5 low mass silicon tracker demonstrator Bettarini, S.; Ratti, L.; Rizzo, G. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
11/2010, Letnik:
623, Številka:
3
Journal Article
Recenzirano
A low material budget silicon demonstrator has been tested by the SLIM5 collaboration with 12
GeV/
c protons at the PS-T9 beam line at CERN. Two devices were placed inside a reference telescope and ...their characteristics were measured. The first was a 4k-Pixel Matrix of Deep N Well MAPS, developed in a 130
nm CMOS technology, providing digital sparsified readout. The other one was a high resistivity double-sided silicon detector, with short strips at a
45
∘
angle to the detector's edge, read out by the FSSR2 chip. In this paper we describe the main features of both sensors. The primary goal of the test was to measure the efficiency and the resolution of the DUTs under different conditions of threshold setting and incident angle of the impinging particles. The data-driven approach of the readout chips has been fully exploited by the DAQ system to take data with a track-based level-1 trigger provided by a pattern matching algorithm with very low latency.
In the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius ...(about 1.5cm), resolution of 10–15μm in both coordinates, low material budget <1%X0, and the ability to withstand a background hit rate of several tens of MHz/cm2. Thanks to an intense R&D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time stamping. Further MAPS performance improvements are currently under investigation with two different approaches: the INMAPS CMOS process, featuring a quadruple well and a high resistivity substrate, and 3D CMOS MAPS, realized with vertical integration technology. In both cases specific features of the processes chosen can improve charge collection efficiency, with respect to a standard DNW MAPS design, and allow to implement a more complex in-pixel logic in order to develop a faster readout architecture. Prototypes of MAPS matrix, suitable for application in the SuperB Layer0, have been realized with the INMAPS 180nm process and the 130nm Chartered/Tezzaron 3D process and results of their characterization will be presented in this paper.
The small angle tile calorimeter in the DELPHI experiment Alvsvaag, S.J.; Bari, M.; Barreira, G. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
04/1999, Letnik:
425, Številka:
1
Journal Article
Recenzirano
Odprti dostop
The Small angle TIle Calorimeter (STIC) provides calorimetric coverage in the very forward region of the DELPHI experiment at the CERN LEP collider. The structure of the calorimeters, built with a ...so-called “shashlik” technique, gives a perfectly hermetic calorimeter and still allows for the insertion of tracking detectors within the sampling structure to measure the direction of the showering particle. A charged-particle veto system, composed of two scintillator layers, makes it possible to trigger on single photon events and provides e–γ separation. Results are presented from the extensive studies of these detectors in the CERN testbeams prior of installation and of the detector performance at LEP.
The front-end chip of the SuperB SVT detector Giorgi, F.; Comotti, D.; Manghisoni, M. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
08/2013, Letnik:
718
Journal Article
Recenzirano
Odprti dostop
The asymmetric e+e− collider SuperB is designed to deliver a high luminosity, greater than 1036cm−2s−1, with moderate beam currents and a reduced center of mass boost with respect to earlier ...B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2MHz per strip, the efficiency of the digital readout remained above 99.8%.
Beam test results for the SuperB-SVT thin striplet detector Fabbri, L.; Comotti, D.; Manghisoni, M. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
08/2013, Letnik:
718
Journal Article
Recenzirano
Odprti dostop
The baseline detector option for the first layer of the SuperB Silicon Vertex Tracker (SVT) is a high resistivity double-sided silicon device with short strips (striplets) at 45° angle to the ...detector's edge. A prototype was tested with a 120GeV/c pion beam in September 2011 at the SPS-H6 test-beam line at CERN. In this paper studies on efficiency, resolution and cluster size are reported.
The Belle II Silicon Vertex Detector comprises four layers of double-sided silicon strip detectors (DSSDs), consisting of ladders with two to five sensors each. All sensors are individually read out ...by APV25 chips with the Origami chip-on-sensor concept for the central DSSDs of the ladders. The chips sit on flexible circuits that are glued on the top of the sensors. This concept allows a low material budget and an efficient cooling of the chips by a single pipe per ladder. We present the construction of the first SVD ladders and results from precision measurements and electrical tests.
Recent measurements of 120 GeV proton extraction by means of a bent silicon crystal at the CERN-SPS accelerator are summarized. The existence of multi-pass extraction has been proven by blocking ...first-pass extraction: using a crystal covered with an amorphous layer, extracted beam with high efficiency was observed, which provides a direct proof for the importance of the multi-pass mechanism. This opens new possibilities in the design and optimization of a bent crystal extraction scheme.
Belle II Silicon Vertex Detector Dutta, D.; Adamczyk, K.; Aziz, T. ...
Journal of instrumentation,
02/2017, Letnik:
12, Številka:
2
Journal Article
Recenzirano
The Belle II experiment at the SuperKEKB asymmetric energy e super(+)e super(-) collider in KEK, Japan will operate at an instantaneous luminosity 40 times larger than that of its predecessor, Belle. ...It is built with an aim of collecting a huge amount of data (50 ab super(-1) by 2025) for precise CP violation measurements and new physics search. Thus, we need an accurate vertex determination and reconstruction of low momentum tracks which will be achieved with the help of vertex detector (VXD). The Belle II VXD consists of two layers of DEPFET pixels ('Pixel Detector') and four layers of double-sided silicon microstrip sensors ('Silicon Vertex Detector'), assembled over carbon fibre ribs. In this paper, we discuss about the Belle II Silicon Vertex Detector, especially its design and key features; we also present its module ('ladder') assembly and testing procedures.
The latest advances in the design and characterization of several pixel sensors developed to satisfy the very demanding requirements of the innermost layer of the SuperB Silicon Vertex Tracker will ...be presented in this paper. The SuperB machine is an electron positron collider operating at the ϒ(4S) peak to be built in the very near future by the Cabibbo Lab consortium. A pixel detector based on extremely thin, radiation hard devices able to cope with rate in the tens of MHz/cm2 range will be the optimal solution for the upgrade of the inner layer of the SuperB tracking system. At present several options with different levels of maturity are being investigated to understand advantages and potential issues of the different technologies: thin hybrid pixels, Deep N-Well CMOS MAPS, INMAPS CMOS MAPS featuring a quadruple well and high resistivity substrates and CMOS MAPS realized with Vertical Integration technology. The newest results from beam test, the outcomes of the radiation damage studies and the laboratory characterization of the latest prototypes will be reported.
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