Abstract
The verification of ASICs through simulation is critical to ensure their successful operation in particle physics detectors and to minimize the number of long and expensive production cycles ...required. Three radiation-tolerant ASICs (HCC, AMAC, and ABC) will perform the front-end readout, monitoring, and control of the ITk Strip charged-particle tracker for the ATLAS detector at the HL-LHC. The Python-based cocotb verification framework is used to design sophisticated tests with contributions from ASIC verification non-experts and students. The verification program includes interactions between multiple ASICs, realistic data flows, operational stress tests, and a focus on mitigation of disruptive Single Event Effects due to radiation.
Abstract
The high-luminosity upgrade to the LHC requires a new silicon-strip charged-particle tracking detector for ATLAS. The HCC (Hybrid Controller Chip) is one of three new radiation-tolerant ...ASICs for this silicon-strip detector. As the interface to multiple binary readout ASICs, the HCC is responsible for buffering and forwarding control signals and readout requests to them as well as serializing their readout data into a 640 Mbps output. All HCCs undergo a suite of tests to verify their analog and digital functionality. The yield for the HCC exceeds the 90% target for production.
Abstract
For the high-luminosity upgrade to the LHC, the ATLAS Inner Detector will be replaced by an all-silicon tracker (ITk) consisting of two systems: pixels and strips. HCC and AMAC are ITk Strip ...ASICs vital for performing the system readout, monitoring, and control. To ensure these ASICs will successfully operate in the high-radiation environment of the HL-LHC, they need to be tested for radiation tolerance, and tests have been performed using both heavy ions and protons. The ASIC designs were shown to protect against single event effects due to radiation.
The HL-LHC, the planned high luminosity upgrade for the LHC, will increase the collision rate in the ATLAS detector approximately a factor of 5 beyond the luminosity for which the detectors were ...designed, while also increasing the number of pile-up collisions in each event by a similar factor. This means that the level-1 trigger must achieve a higher rejection factor in a more difficult environment. This presentation discusses the challenges that arise in this environment and strategies being considered by ATLAS to include information from the tracking systems in the level-1 decision. The main challenges involve reducing the data volume exported from the tracking system for which two options are under consideration: a region of interest based system and an intelligent sensor method which filters on hits likely to come from higher transverse momentum tracks.
The process gg → H → WW* → llvv is one of the most sensitive and challenging Higgs search channels at hadron colliders. This channel is also sensitive to a variety of new physics scenarios. This ...paper describes two searches using multivariate techniques to separate a potential Higgs signal from the much larger continuum q → WW production using 1.1 fb-1 of 1.96 TeV p collisions recorded with the CDF detector.
Observation of B → φ K and B → φ K Briere, R. A.; Chen, G. P.; Ferguson, T. ...
Physical review letters,
04/2001, Letnik:
86, Številka:
17
Journal Article
From electron-positron collision data collected with the CLEO detector operating at Cornell Electron Storage Ring near sqrts=10.6 GeV, improved measurements of the branching fractions for tau decays ...into three explicitly identified hadrons and a neutrino are presented as B(tau(-)-->pi(-)pi(+)pi(-)nu(tau))=(9.13+/-0.05+/-0.46)%, B(tau(-)-->K-pi(+)pi(-)nu(tau))=(3.84+/-0.14+/-0.38) x 10(-3), B(tau(-)-->K-K+pi(-)nu(tau))=(1.55+/-0.06+/-0.09) x 10(-3), and B(tau(-)-->K-K+K-nu(tau))<3.7 x 10(-5) at 90% C.L., where the uncertainties are statistical and systematic, respectively.
The CMS data acquisition system is designed to build and filter events originating from 476 detector data sources at a maximum trigger rate of 100 kHz. Different architectures and switch technologies ...have been evaluated to accomplish this purpose. Events will be built in two stages: the first stage will be a set of event builders called front-end driver (FED) builders. These will be based on Myrinet technology and will pre-assemble groups of about eight data sources. The second stage will be a set of event builders called readout builders. These will perform the building of full events. A single readout builder will build events from about 60 sources of 16 kB fragments at a rate of 12.5 kHz. In this paper, we present the design of a readout builder based on TCP/IP over Gigabit Ethernet and the refinement that was required to achieve the design throughput. This refinement includes architecture of the readout builder, the setup of TCP/IP, and hardware selection.
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