The band-to-band tunneling hot-electron (BBHE) programming characteristics of the 2 bit/cell p-channel bandgap-engineered silicon-oxide-nitride-oxide-semiconductor (SONOS) (H. T. Lue, et al., in IEDM ...Tech. Diag., p. 331) device are extensively studied. The lateral BBHE profile is extracted by fitting the experimental current-voltage (I-V) characteristics with 2-D simulation. The results suggest that, after BBHE injection, the local channel potential barrier is reduced, which, in turn, raises the Vt of the p-channel device. The 2 bit/cell operation methods and second-bit effect (2 bit interaction) are examined. The effects of channel-length scaling, junction profile, and effective oxide thickness of the gate stack are also addressed
For the first time, we can directly investigate the charge transport and intra-nitride behaviors of SONOS-type devices by exploiting the gate-sensing and channel-sensing (GSCS) method. Our results ...clearly indicate that for electron injection (+FN program), the electron centroid migrates from the bottom toward the nitride center, whereas for hole injection (-FN erase), holes first recombine with the bottom electrons and then gradually move upward. For the electron de-trapping processes under -V G stressing, the trapped electrons de-trap first from the bottom portion of nitride. We also develop a method to distinguish the electron de-trapping and hole injection erasing methods by comparing the erasing current density (J) versus the bottom oxide electric field (E). At short-term high-temperature baking, the electrons move from the top portion toward the bottom portion, and this intra-nitride transport becomes more significant for a thicker nitride. On the other hand, after long-term baking, the charge loss mainly comes from the bottom portion of nitride.
The advantage of using extremely-thin body (ETB, Tsi=3nm) device has been demonstrated in a 3D NAND Flash test chip. Net P/E memory window gain of >1.3V is observed for devices using ETB poly-Si. ...This substantial gain can be explained by the "quantum confinement" that raises effective Si bandgap and in turn reduces the tunneling barrier height. Simulation model has been validated and it shows equivalent barrier height reduction of ~0.16eV and 0.07eV for electron and hole, respectively for Tsi=3nm. Meanwhile, the extremely-thin body poly silicon channel can improve S.S. to nearly 250mV/dec, which is close to bulk 2D Flash devices. However, the Idsat is degraded to only 160nA for Tsi=3nm, which is attributed to the larger effective mass or higher contact resistance. The degraded Idsat can be accommodated by lower Isense<30nA for page buffer circuit tuning. Random telegraph noise (RTN) is significantly reduced by extremely-thin body, and it shows tighter program-verify (PV) distribution in the MLC/TLC operation.
NOR Flash has stopped scaling for many years. However, recently there are increasingly new demands of NOR Flash in various 5G and IoT applications or wearable devices that strongly require new ...technology advancement of NOR. In this work, we developed a new vertical 2T (V2T) NOR Flash architecture that provides not only scaling capability but also low-power solutions. We leveraged the process of standard 3D NAND to develop a vertical 2T NOR that produces even smaller cell size than conventional planar 1T NOR. Advanced high-K metal-gate (HK/MG) integration is developed to provide high-performance BE-MANOS charge-trapping device with excellent 1M endurance and retention reliability. The 2T NOR architecture provides low-voltage read (~1V) that is compatible with advanced CMOS circuits without charge pumping to save power. We also suggest future technology extensions of the V2T NOR by adopting the ferroelectric memory devices (FeFET) and the 3DIC chiplets integration to broaden the applications fields of NOR technology in embedded Flash and computing in memory (CIM).
We developed a Monte Carlo simulation method to accurately predict the large-density NAND flash product memory window based on several device parameters collected in the small-array test element ...group (TEG). The required parameters include the ISPP slope, intrinsic Vt distribution sigma, program noise, random telegraph noise (RTN), and various interference ratios. All these parameters can be collected from the wafer acceptance test (WAT) of a small-array TEG. The simulation methodology is to randomly generate a Vt distribution ensemble that resembles the product memory cell. Programming simulation of each memory cell considers the programming distribution and various fluctuation factors during ISPP programming and verification. Experimental data of a fabricated 3D NAND test chip are compared with the simulation results, and show excellent consistency. This novel methodology not only provides memory product window from device parameters of TEG, but also emulates various MLC programming algorithms to optimize the product-level memory window.
We report an extremely scaled HC 3D NAND device with large memory window in this paper. The proposed cell area (0.009μm 2 /layer) is only ~ 32% of the standard GAA 3D NAND cell area, while it can ...produce very large gt; 10V Vt memory window with excellent 100K endurance. We also study the size effect of HC device. It is found that the larger (taller) HC device may easily suffer parasitic edge leakage effect that causes programming saturation issue. A "wake-up" effect by an initial strong -FN erasing can introduce gate injected electrons that electrically suppress the parasitic edge and in turn "wake-up" the device to produce larger programming window. On the other hand, the smaller HC device already shows excellent memory window without the need of wake-up. Good post-cycled retention and RTN performance are demonstrated for an extremely scaled, "hero" HC device. Our results suggest a promising path of 3D NAND device to enjoy both aggressive dimension scaling and large memory window.
For the first time, we've fabricated a confined nitride (SiN) trapping layer device for 3D NAND Flash and demonstrated excellent post-cycling retention performances. The key process step is to ...develop a uniform sidewall lateral recess in the 3D stack, followed by a SiN pull back process to isolate the SiN trapping layer in a self-aligned way. Excellent retention with only ~600mV shift of charge loss (out of initial 7V window) after 125C 1-week high-temp baking for a post 1K cycled device was obtained. It is far superior to the control sample without confined SiN structure. Arrhenius analysis at various baking temperatures shows that the retention may pass> 100 years at 60C, and is even longer at room temperature. The device has potential to meet the low-cost long-retention archive memory applications.
In this paper, we report the junction breakdown instability of a depletion-mode high-voltage NMOSFET (DN) used in the NAND Flash peripheral circuit. Such DN device needs to sustain the highest ...voltage (>30V) during NAND Flash programming. We observed instability of the junction breakdown in the product chip. Electrical measurement shows that the first measured breakdown voltage (BV DSS ) from virgin state is usually lower than that after stress, which is called the "walk-out" effect. The walk-out effect can be recovered by a high-temperature baking, indicating it's not a permanent damage. TCAD simulation suggests that gate edge hole trapping by the band-to-band tunneling injection is the root cause of such walk-out effect. The conventional layout structure of the DN has a large overlap of the buried-channel N-type doping with the light-doped drain (LDD), leading to the worse walk-out effect than normal HV NMOS. To suppress this effect, we propose an optimal layout design method of DN to avoid the overlap of N-type buried-channel doping with the LDD. Experimental results show very good improvements of BV DSS with acceptable transistor performances.
A new method to probe the trap vertical location for nitride-trapping devices is proposed. This method requires only measuring the time dependence of gate injection at various gate voltages on a ...single wafer. The transient current (J) and the instantaneous electric field (E) across the top oxide can be directly obtained based on various cases of trap location. Comparisons can be made to check which case has the best consistency for the J versus E behaviors. The only assumption in this method is that the transient current J and the instantaneous E field should follow a consistent tunneling relationship at different gate voltages. The experimental results show unequivocally that electrons are trapped at the interface between top oxide and nitride for oxide grown by thermal conversion. However, for the direct-deposited top oxide the electrons are more spatially distributed in the nitride. This method is a simple and convincing tool to detect the nitride trap vertical location.
A body-tied FinFET bandgap engineered (BE)-silicon-oxide-nitride-oxide-silicon (SONOS) nand Flash device is successfully demonstrated for the first time. BE-SONOS device with a BE oxide-nitride-oxide ...barrier is integrated in the FinFET structure with a 30-nm fin width. FinFET BE-SONOS can overcome the unsolvable tradeoff between retention and erase speed of the conventional SONOS. Compared with the current floating-gate Flash devices, FinFET BE-SONOS provides both retention and erase-speed performance, while eliminating the scaling limitations and is, thus, an important candidate for further scaling of nand Flash
